Methods and apparatus for sharing memory bandwidth

An apparatus, comprising:

• a processor;
• one or more direct memory access (DMA) engines;
• a memory;
• an arbiter for coupling the processor and one or more DMA engines to the memory, thereby defining a memory bandwidth;
• and
• logic, coupled to the memory and arbiter, and adapted to:
• share memory bandwidth between the processor and one or more DMA engines;
• provide memory bandwidth to a DMA engine;
• start a data transfer between the memory and the DMA engine, via the memory bandwidth, based on a first preemption boundary value, wherein the data transfer may be preempted after transferring an amount of data equal to an integral multiple of the first preemption boundary value;
• while transferring data between the memory and DMA engine, determine whether a request for memory bandwidth is received from the processor, wherein the processor is in an interrupt state;
• and
• if a request for memory bandwidth is received from the processor in the interrupt state, adjust the first preemption boundary value such that the adjusted preemption boundary value enables the processor to receive memory bandwidth sooner than the first preemption boundary value.

A method, comprising:

• sharing memory bandwidth between a processor and one or more direct memory access (DMA) engines;
• providing memory bandwidth to a DMA engine;
• starting a data transfer between a memory and the DMA engine, via the memory bandwidth, based on a first and second preemption boundary values, wherein the data transfer may be preempted after transferring an amount of data equal to an integral multiple of at least one of the first and second preemption boundary values and wherein the first preemption boundary value is smaller than the second preemption boundary value;
• determining whether an amount of data equal to an integral multiple of at least one of the first and second preemption boundary values is transferred;
• if an amount of data equal to an integral multiple of the first preemption boundary value is transferred, determining whether a request for memory bandwidth is received from a processor in an interrupt state;
• and
• if a request for memory bandwidth is received from a processor in an interrupt state, providing memory bandwidth to the processor in the interrupt state.

An apparatus, comprising:

• a processor;
• one or more direct memory access (DMA) engines;
• a memory;
• an arbiter for coupling the processor and one or more DMA engines to the memory, thereby defining a memory bandwidth;
• and
• logic, coupled to the memory and arbiter, and adapted to:
• share memory bandwidth between the processor and one or more DMA engines;
• provide memory bandwidth to a DMA engine;
• start a data transfer between the memory and the DMA engine, via the memory bandwidth, based on a first and second preemption boundary values, wherein the data transfer may be preempted after transferring an amount of data equal to an integral multiple of at least one of the first and second preemption boundary values and wherein the first preemption boundary value is smaller than the second preemption boundary value;
• determine whether an amount of data equal to an integral multiple of at least one of the first and second preemption boundary values is transferred;
• if an amount of data equal to an integral multiple of the first preemption boundary value is transferred, determine whether a request for memory bandwidth is received from the processor in an interrupt state;
• and
• if a request for memory bandwidth is received from the processor in an interrupt state, provide memory bandwidth to the processor in the interrupt state.