Methods and arrangements to manage on-chip memory to reduce memory latency

An apparatus for controlling data stored on a chip by a software application, comprising:

• an on-chip memory comprising a block for allocation to the software application, the on-chip memory sharing the chip with a processor and a cache;
• a controller to allocate the block of the on-chip memory for the data in response to an instruction initiated by the software application, the instruction being associated with the data, and to access the block of the on-chip memory to obtain the data in response to a request for the data by the processor;
• and
• a driver coupled with the on-chip memory and responsive to the controller to transfer the data from the main memory to store the data in the block of the on-chip memory based upon an indication from the software application.

A machine-accessible medium containing a program for controlling data stored in an on-chip memory sharing a chip with a processor and a cache by a software application, which, when executed, performs operations, the operations comprising:

• allocating within the on-chip memory of the chip a block of processor memory region for the data in response to an instruction initiated by the software application, the instruction being associated with the data;
• transferring the data from a main memory to the block within the on-chip memory via a driver based upon an indication from the software application, the driver to transfer the data from the main memory and store the data in the block of the on-chip memory;
• and
• accessing the block of the on-chip memory to obtain the data in response to a request for the data by the processor.