US 2006/0155521 A1 · Method and apparatus for supporting verification, and computer product

Abstract

In a verification supporting apparatus, when an obtaining unit obtains a verification scenario, a substituting unit substitutes an undefined value for a variable value in the verification scenario. A first executing unit executes a logic simulation using an input pattern. From a result of the logic simulation, a determining unit generates code-coverage upper-limit information. A setting unit sets input patterns by giving an arbitrary logic value to the variable value. A second executing unit executes a logic simulation using the input patterns set. A generating unit generates code coverage from the input patterns set. A calculating unit calculates a level of achievement of the code coverage with respect to the code-coverage upper-limit information.

Claims12

Dependent claims

A computer-readable recording medium that stores therein a computer program for supporting verification, the computer program making a computer execute:

obtaining circuit information and a verification scenario, the circuit information of a verification target circuit, the verification scenario including a variable value for verifying the verification target circuit;
executing a logic simulation by giving the verification scenario to the circuit information;
and
determining, based on a result of the logic simulation, code-coverage upper-limit information that indicates a portion to which the variable value is propagated in the circuit information.

1 more element

Dependencies are inferred from the claim text.

Method and apparatus for supporting verification, and computer product

Life of this patent

Method and apparatus for supporting verification, and computer product

Life of this patent

Abstract

Claims12