CMOS transistors and methods of forming same

A semiconductor structure formed in the process of fabricating a CMOS transistor structure prior to an activating anneal, comprising:

• a semiconductor substrate having an P-type dopant region to support an NMOS transistor and a N-type dopant region to support a PMOS transistor, each of the N-type dopant and P-type dopant regions having an overlying gate stack including a conductive gate;
• a layer of insulating material over the semiconductor substrate and gate stack;
• lightly-doped extension regions in the semiconductor substrate adjacent each gate stack;
• an interfacial layer of nitrogen formed at the interface of the lighted-doped extension regions and the layer of insulating material;
• source and drain regions in the semiconductor substrate adjacent to each of the gate stacks;
• and
• a capping layer of contiguous silicon nitride over the semiconductor substrate and each of the gate stacks.

A structure formed in the fabrication of a CMOS transistor semiconductor chip prior to an activating thermal anneal, comprising:

• a semiconductor substrate having a P-type dopant region to support an NMOS transistor and an N-type dopant region to support a PMOS transistor, each of the N-type dopant and P-type dopant regions having an overlying gate stack including a conductive gate supporting an oxide sidewall;
• lightly-doped extension regions in the semiconductor substrate adjacent each gate stack, the lightly-doped extension regions in the N-type dopant region comprising a P-type dopant having a dopant concentration in the range of about 1-2 e20 atoms/cm3;
• a layer of silicon oxide over the lightly doped extension regions;
• an interfacial layer of nitrogen at the interface between the layer of silicon oxide and the lightly-doped extension regions, the interfacial layer of nitrogen having an atomic nitrogen concentration in the range of 2-15 atomic percent;
• source and drain regions in the semiconductor substrate adjacent to each of the gate stacks, the source and drain regions in the N-type dopant region comprising a P-type dopant having a concentration in the range of about 1-2 e20 atoms/cm3;
• and
• a capping layer of contiguous silicon nitride having a thickness in the range of about 200-1000 angstroms over the semiconductor substrate and each of the gate stacks.