Control device and control method capable of external synchronization

An externally-synchronizable controller comprising means for generating a synchronization interrupt signal when a synchronizing signal output from the outside, such as from a host controller, is input during a given cycle;

• means which generates a control cycle signal used for effecting control processing during a given cycle;
• means for generating a control interrupt signal when said control cycle signal is input;
• means which receives an input of data from said host controller and outputs data to said host controller;
• a synchronization interrupt processing section which performs synchronization interrupt processing when said synchronization interrupt signal is input;
• and a control interrupt processing section which performs control interrupt processing when said control interrupt signal is input, wherein
• said synchronization interrupt processing section activates said means for generating a control cycle signal to thus generate said control interrupt signal, thereby executing control interrupt processing in synchronism with a synchronizing signal from the outside.

An externally-synchronizable control method for use with a controller comprising means for generating a synchronization interrupt signal when a synchronizing signal output from the outside, such as from a host controller, is input during a given cycle;

• means which generates a control cycle signal used for effecting control processing during a given cycle;
• means for generating a control interrupt signal when said control cycle signal is input;
• means which receives an input of data from said host controller and outputs data to said host controller;
• a synchronization interrupt processing section which performs synchronization interrupt processing when said synchronization interrupt signal is input;
• and a control interrupt processing section which performs control interrupt processing when said control interrupt signal is input, said control method comprising:
• inputting to an interrupt circuit (21) a synchronizing signal (S10) generated during a given cycle by said host controller;
• generating a synchronization interrupt signal (S20) by means of said interrupt circuit 21;
• activating a control cycle generation circuit and causing said control cycle generation circuit to output a control cycle signal (S22) to said interrupt circuit (21);
• generating a control interrupt signal (S21) and said synchronization interrupt signal (S20) by means of said interrupt circuit (21), and outputting said control interrupt signal and said synchronization interrupt signal to a CPU (20);
• and
• activating a control cycle generation circuit, by means of software, which causes a synchronization interrupt processing section to start control interrupt processing.