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US 2006/0152994 A1Published application
Timer lockout circuit for synchronous applications
AssigneeInternational Business Machines Corporation
InventorsMark Jacunski, Alan Norris, Samuel Weinstein
Life of this patent
Estimating the term…
Abstract
A SDRAM. The SDRAM including: at least one bank of DRAM cells; the SDRAM operable to a first specification defined by a first clock frequency, a first write recovery time and a first time interval for precharge to row address strobe; and means for programming the SDRAM operable to a second specification defined by a second clock frequency, a second write recovery time and a second time interval for precharge to row address strobe.
Claims18
A timer lockout circuit comprising:
- a first delay circuit for receiving and delaying a first timing signal;
- a first circuit for receiving said first timing signal from said first delay circuit and for latching said first timing signal;
- a programmable timing circuit for receiving said first timing signal from said first circuit and for delaying said first timing signal by a programmable time interval;
- a one-shot generator for receiving said first timing signal from said programmable timing circuit and for generating a set signal;
- a second circuit for receiving said set signal from said one-shot generator and for latching said set signal;
- a third circuit for receiving a second timing signal and for latching said second timing signal;
- a combinational logic circuit for receiving said set signal from said second circuit and for receiving said second timing signal from said third circuit and for generating a third timing signal;
- and
- a second delay circuit for receiving and delaying said third timing signal and for simultaneously resetting said first circuit, said second circuit and said third circuit after delaying said third timing signal.
6 more elements
A timer lockout circuit comprising:
- first means for receiving a first timing signal from a first delay circuit and for latching said first timing signal;
- second means for receiving said first timing signal from said first means and for delaying said first timing signal by a programmable time interval;
- third means for receiving said first timing signal from said second means and for generating a set signal;
- fourth means for receiving said set signal from said third means and for latching said set signal;
- fifth means for receiving a second timing signal and for latching said second timing signal;
- sixth means for receiving said set signal from said fourth means and for receiving said second timing signal from said fifth means and for generating a third timing signal;
- and
- seventh means for simultaneously resetting said first means, said fourth means and said fifth means.
5 more elements
A method for delaying a timing signal, comprising:
- providing a delay circuit for receiving and delaying a first timing signal;
- providing a first circuit for receiving said first timing signal from said first delay circuit and for latching said first timing signal;
- providing a programmable timing circuit for receiving said first timing signal from said first circuit and for delaying said first timing signal by a programmable time interval;
- providing a one-shot generator for receiving said first timing signal from said programmable timing circuit and for generating a set signal;
- providing a second circuit for receiving said set signal from said one-shot generator and for latching said set signal;
- providing a third circuit for receiving a second timing signal and for latching said second timing signal;
- providing a combinational logic circuit for receiving said set signal from said second circuit and for receiving said second timing signal from said third circuit and for generating a third timing signal;
- and
- providing a second delay circuit for receiving and delaying said third timing signal and for simultaneously resetting said first circuit, said second circuit and said third circuit after delaying said third timing signal.
6 more elements
Dependencies are inferred from the claim text.