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US 2006/0152988 A1Published application
Memory component having a novel arrangement of the bit lines
AssigneeInfineon Technologies AG
InventorsFlorian Schnabel, Helmut Schneider
Life of this patent
Estimating the term…
Abstract
A memory component comprises a plurality of bit lines, on which memory cells are arranged, and a plurality of sense amplifiers, which are arranged in a row, each sense amplifier being connected to two bit lines. A bit line which is connected to a first sense amplifier in the row is arranged directly adjacent to a bit line which is connected to a second sense amplifier in the same row.
Claims20
A memory component, comprising:
- a plurality of bit lines on which memory cells are arranged;
- and
- a plurality of sense amplifiers arranged in a first row, each sense amplifier connected to two bit lines of the plurality of bit lines, wherein a first bit line connected to a first sense amplifier in the first row is arranged directly adjacent to a second bit line connected to a second sense amplifier in the first row.
A memory component, comprising:
- a first plurality of memory cells arranged on a first word line and on a first plurality of bit lines which are arranged substantially perpendicularly to the first word line;
- and
- a first plurality of sense amplifiers arranged in a first row which is substantially parallel to the first word line, wherein at least two adjacent sense amplifiers are respectively connected to at least two adjacent bit lines.
A memory component, comprising:
- a plurality of bit lines arranged in a plurality of columns;
- a plurality of word lines arranged in a plurality of rows substantially perpendicularly to the plurality of columns;
- a plurality of memory cells are disposed at respective intersections of each bit line and each word line;
- and
- a plurality of sense amplifiers arranged in a plurality of rows, wherein the sense amplifiers of each row are arranged into groups of adjacent sense amplifiers which are connected to respective adjacent bit lines, wherein each group comprises at least two adjacent sense amplifiers and a corresponding number of adjacent bit lines.
2 more elements
Dependencies are inferred from the claim text.