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AssigneeMicron Technology, Inc.
InventorsChristopher Johnson, Brian Johnson
Estimating the term…
A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low write latency mode. The logic circuit receives a first signal indicative of whether the high-power, low write latency mode has been enabled, a second signal indicative of whether a row of memory cells in the memory device is active, a third signal indicative of whether the memory device is being operated in a power down mode, and a fourth signal indicative of whether read transmitters in the memory device are active. The logic circuit maintains power to the write receivers whenever the high-power, low write latency mode has been enabled if a row of memory cells in the memory device is active, the memory device is not being operated in the power down mode, and the read transmitters in the memory device are not active.
A write receiver control circuit for use in a memory device to operate a plurality of write receivers in either a high-power, low write latency mode or a low-power, high write latency mode, the write receiver control circuit comprising a logic circuit receiving a first signal indicative of whether the high-power, low write latency mode has been enabled, and a second signal indicative of whether read transmitters are active, the logic circuit being operable responsive to the first signal indicating that the high-power, low write latency mode has been enabled to apply power to the write receivers when the read transmitters are not active regardless of whether the write receivers are active, and to remove power from the write receivers when the read transmitters are active, the logic circuit further being operable responsive to the first signal indicating that the high-power, low write latency mode has not been enabled to apply power to the write receivers when the write receivers are active and the read receivers are not active, and to remove power from the write receivers when either the write receivers are not active or the read transmitters are active.
2-59. (canceled)
Dependencies are inferred from the claim text.