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US 2006/0152962 A1Published application
Integrated DRAM-NVRAM multi-level memory
AssigneeMicron Technology, Inc.
InventorsArup Bhattacharyya, Leonard Forbes
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AssigneeMicron Technology, Inc.
InventorsArup Bhattacharyya, Leonard Forbes
Estimating the term…
An integrated DRAM-NVRAM, multi-level memory cell is comprised of a vertical DRAM device with a shared vertical gate floating plate device. The floating plate device provides enhanced charge storage for the DRAM part of the cell through the shared floating body in a pillar between the two functions. The memory cell is formed in a substrate with trenches that form pillars. A vertical wordline/gate on one side of a pillar is used to control the DRAM part of the cell. A vertical trapping layer on the other side of the pillar stores one or more charges as part of the floating plate device and to enhance the DRAM function through the floating body between the DRAM and floating plate device. A vertical NVRAM wordline/control gate is formed alongside the trapping layer and is shared with an adjacent floating plate device.
A method for operation of an integrated DRAM-NVRAM cell having a DRAM function and a NVRAM function, the cell comprising a DRAM gate, a NVRAM control gate, a DRAM source region, a NVRAM source region, a shared drain region, and a bitline coupled to the shared drain region, the method comprising:
The method of claim I wherein the DRAM function operates as an access device for the NVRAM function.
The method of claim I wherein the DRAM source region and the NVRAM source region are formed in a substrate.
A method for operation of an integrated DRAM-NVRAM cell having a DRAM function and a NVRAM function, the cell formed by a pillar between two trenches and comprising a vertical DRAM gate, a vertical NVRAM control gate, a DRAM source region, a NVRAM source region, a shared drain region at the top of the pillar, and a bitline coupled to the shared drain region, the method comprising:
A method for operation of an integrated DRAM-NVRAM cell having a DRAM function and a NVRAM function, the cell formed by a pillar between two trenches and comprising a vertical DRAM gate, a vertical NVRAM control gate, a DRAM source region, a NVRAM source region, a shared drain region at the top of the pillar, and a bitline coupled to the shared drain region, the method comprising:
Dependencies are inferred from the claim text.