ESD protection unit with ability to enhance trigger-on speed of low voltage triggered PNP

An ESD protection unit for providing ESD path from a plurality of I/O pad either to a high voltage node VDD pin or a low voltage node VSS pin, the unit comprising:

• a first ESD detection circuit connecting to the I/O pad, having a first RC delay interconnected between the VDD pin and the VSS pin, and a plurality of N-MOS transistors each having a gate connecting to said first RC delay, and a source connecting to the I/O pad;
• a plurality of N-trigger LVTPNP devices each including an emitter connecting to the VDD pin, a collector connecting to the I/O pad, and an N-trigger node connecting to a drain of a corresponding NMOS transistor wherein the N-trigger LVTPNP devices shut down in a normal operation and are speedily triggered on by a higher potential-level output of the first ESD detection circuit when an ESD stress occurs between the I/O pad and the VDD pin;
• a second ESD detection circuit connecting to the I/O pad, having a second RC delay interconnected between the VSS pin and the VDD pin, and a plurality of PMOS transistors each having a gate connecting to said second RC delay, and a source connecting to the I/O pad;
• and
• a plurality of P-trigger LVTPNP devices each including an emitter connecting to the I/O pad, a collector connecting to the VSS pin, and a P-trigger node connecting to a drain of the corresponding NMOS transistor wherein the P-trigger LVTPNP devices shut down in a normal operation and are speedily triggered on by a lower potential-level output of the first ESD detection circuit when an ESD stress occurs between the I/O pad and the VSS pin.