Scan driver for selectively performing progressive scanning and interlaced scanning and a display using the same

A display, comprising:

• a pixel array including a plurality of pixels;
• a scan driver for transmitting a scan signal and an emission control signal to the pixel array and selectively performing progressive scanning and interlaced scanning;
• and
• a data driver for transmitting data to a pixel selected by the scan signal of the scan driver,
• wherein the scan driver comprises:
• a shift register for receiving a start pulse and a clock signal and outputting data at intervals of a cycle of the clock signal;
• an odd line selection unit for receiving an output signal of an odd-numbered flip-flop of the shift register and an odd line control signal and performing a logical operation on the received signals to generate an odd scan signal;
• and
• an even line selection unit for receiving an output signal of an even-numbered flip-flop of the shift register and an even line control signal and performing a logical operation on the received signals to generate an even scan signal.

A scan driver that selectively performs progressive scanning and interlaced scanning, comprising:

• a shift register for receiving a start pulse and a clock signal and outputting data at intervals of half of a cycle of the clock signal;
• a mode selection unit for receiving an output signal of a flip-flop of the shift register and performing a logical operation on the output signal of the flip-flop in response to a mode selection signal;
• an odd line selection unit for selecting an output signal of an odd-numbered flip-flop or an output signal of the mode selection unit in response to an odd line control signal;
• and
• an even line selection unit for selecting an output signal of an even-numbered flip-flop or the output signal of the mode selection unit in response to an even line control signal.

A scan driver that selectively performs progressive scanning and interlaced scanning, comprising:

• a shift register including a plurality of flip-flops connected in series, wherein odd-numbered flip-flops sample an input signal and output the sampled signal on a rising edge of a clock signal, and even-numbered flip-flops sample an input signal and output the sampled signal on a falling edge of the clock signal;
• a mode selection unit for performing a logical OR operation on output signals of adjacent flip-flops or masking the output signals of the flip-flops in response to a mode selection signal;
• an odd line selection unit for selecting an output signal of an odd-numbered flip-flop or an output signal of the mode selection unit in response to an odd line control signal;
• and
• an even line selection unit for selecting an output signal of an even-numbered flip-flop or the output signal of the mode selection unit in response to an even line control signal.