Latch circuit, 4-phase clock generator, and receiving circuit

A 4-phase clock generator comprising:

• a first latch circuit that operates based on a clock signal supplied from an outside source, and includes a first data reading unit and a first data holding unit;
• and
• a second latch circuit that operates based on the clock signal, and includes a second data reading unit and a second data holding unit;
• wherein
• the first data reading unit
• reads both a first input data and a second input data that are output from the second latch circuit via a first connection node and a second connection node, respectively, and
• outputs both a first output data and a second output data, based on both the first input data and the second input data, to the second latch circuit via a third connection node and a fourth connection node, respectively,
• the second data reading unit
• reads both a third input data and a fourth input data that are output from the first latch circuit via the third connection node and the fourth connection node, respectively, and
• outputs both a third output data and a fourth output data, based on both the third input data and the fourth input data, to the first latch circuit via the second connection node and the first connection node, respectively, wherein the first output data corresponds to the third input data, the second output data corresponds to the fourth input data, the third output data corresponds to the second input data, and the fourth output data corresponds to the first input data,
• both the first input data and the second input data are differential signals, and both the third input data and the fourth input data are differential signals,
• both the first output data and the second output data are differential signals that have phases that are inverted, and both the third output data and the fourth output data are differential signals that have phases that are inverted,
• the first data holding unit holds both the first output data and the second output data, and the second data holding unit holds both the third output data and the fourth output data, and
• 4-phase signals that have phases that are shifted by 90 degree are output via the first connection node, the second connection node, the third connection node, and the fourth connection node.

A receiving circuit comprising:

• a 4-phase clock generator;
• and
• an analog-digital (A/D) converter, wherein
• the 4-phase clock generator includes
• a first latch circuit that operates based on a clock signal supplied from an outside source, and includes a first data reading unit and a first data holding unit;
• and
• a second latch circuit that operates based on the clock signal, and includes a second data reading unit and a second data holding unit,
• the first data reading unit
• reads both a first input data and a second input data that are output from the second latch circuit via a first connection node and a second connection node, respectively, and
• outputs both a first output data and a second output data, based on both the first input data and the second input data, to the second latch circuit via a third connection node and a fourth connection node, respectively,
• the second data reading unit
• reads both a third input data and a fourth input data that are output from the first latch circuit via the third connection node and the fourth connection node, respectively, and
• outputs both a third output data and a fourth output data, based on both the third input data and the fourth input data, to the first latch circuit via the second connection node and the first connection node, respectively, wherein the first output data corresponds to the third input data, the second output data corresponds to the fourth input data, the third output data corresponds to the second input data, and the fourth output data corresponds to the first input data,
• both the first input data and the second input data are differential signals, and both the third input data and the fourth input data are differential signals,
• both the first output data and the second output data are differential signals that have phases that are inverted, and both the third output data and the fourth output data are differential signals that have phases that are inverted,
• the first data holding unit holds both the first output data and the second output data, and the second data holding unit holds both the third output data and the fourth output data,
• a first signal, a second signal, a third signal, and a fourth signal are output via the fourth connection node, the third connection node, the first connection node, and the second connection node, the second signal having phase that is shifted by 180 degree with respect to the first signal, the third signal having phase that is shifted by 90 degree with respect to the first signal, and the fourth signal having phase that is shifted by 270 degree with respect to the first signal, and
• the A/D converter outputs desired digital signals based on a RF signal that is input to the receiving circuit, the first signal, the second signal, the third signal, and the fourth signal.