Multi-threshold MOS circuits

An integrated circuit comprising at least one multi-threshold flip-flop, each multi-threshold flip-flop comprising:

• a master latch comprised of high threshold (HVT) transistors;
• a slave latch comprised of low threshold (LVT) transistors;
• and
• at least one control switch operative to enable or disable the LVT transistors.

An integrated circuit comprising at least one multi-threshold flip-flop, each multi-threshold flip-flop comprising:

• a master latch comprised of an input buffer formed with low threshold (LVT) transistors and a first latch circuit formed with LVT transistors;
• a slave latch comprised of a second latch circuit formed with high threshold (HVT) transistors and an output driver formed with LVT transistors;
• and
• at least one control switch operative to enable or disable the LVT transistors for the input buffer, the first latch circuit, and the output driver.

An electronic device comprising at least one multi-threshold metal oxide semiconductor (MOS) circuit, each multi-threshold MOS circuit comprising:

• a first circuit comprised of low threshold (LVT) transistors;
• a second circuit comprised of high threshold (HVT) transistors;
• and
• at least one control switch operative to enable or disable the LVT transistors.