Shared bond pad for testing a memory within a packaged semiconductor device

A system comprising:

• a memory device configured to store digital data;
• a command register configured to receive a plurality of command signals for control of the memory device;
• an external terminal configured to receive serial data;
• a plurality of digital logic devices coupled between the external terminal and the command register, the plurality of digital logic devices configured to receive the serial data from the external terminal and to generate the plurality of command signals responsive to the serial data;
• and
• a semiconductor device package configured to include the memory device, the plurality of digital logic devices, and at least part of the external terminal.

A method of testing a first integrated circuit in a semiconductor device package, the method comprising:

• serially receiving a plurality of command signals at a single external terminal of the semiconductor device package;
• converting the serially received plurality of command signals to parallel data;
• conveying the parallel data to a command register;
• affecting the first integrated circuit using the parallel data conveyed to the command register;
• and
• using the single external terminal for conveying data to a second integrated circuit within the semiconductor device package.

A method of operating a memory device included in a semiconductor device package, the method comprising:

• receiving a serial data signal at an external terminal of the semiconductor device package;
• conveying the received serial data signal to a plurality of digital logic devices configured to generate a command signal responsive to the received serial data;
• receiving the generated command signal in a parallel format at a command register;
• and
• operating the memory device responsive the command signal received at the command register.

A system comprising:

• means for receiving a serial data signal at a semiconductor device package;
• means for converting the received serial data signal into a command in a parallel format, the command being configured to control operation of a memory device;
• and
• means for conveying the command into a register of the memory device within the semiconductor device package.

A system comprising:

• shared means for serially receiving a command signal at a semiconductor device package, and for receiving first parallel data at the semiconductor device package;
• means for converting the serially received command signal to second parallel data;
• means for conveying the second parallel data to a command register;
• means for testing a first integrated circuit within the semiconductor device package using the second parallel data conveyed to the command register, in a first mode;
• means for changing from the first mode to a second mode;
• and
• means for operating a second integrated circuit within the semiconductor device package responsive to the first parallel data in the second mode.