Self-aligned process for nanotube/nanowire FETs
AssigneeInternational Business Machines Corporation
InventorsPhaedon Avouris, Roy Carruthers, Jia Chen, Christophe Detavernier, Christian Lavoie, Hon-Sum Wong
Life of this patent
Estimating the term…
Abstract
A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device.
Claims31
A semiconductor structure comprising:
- a substrate comprising at least one gate region located thereon, said at least one gate region comprising a layer of at least one one-dimensional nanostructure;
- and
- a metal carbide contact located on a surface of said substrate that is aligned to an edge of said layer of at least one one-dimensional nanostructure.
A method of fabricating a semiconductor substrate comprising the steps of:
- providing a structure that includes at least one gate stack on a surface of a layer of at least one one-dimensional nanostructure;
- forming a source/drain metal on said structure including at least said layer of at least one one-dimensional nanostructure;
- and
- forming a metal carbide by reacting said source/drain metal with said layer of at least one one-dimensional nanostructure.
The method of 22 wherein said substrate comprises a semiconductor layer and a dielectric layer, said dielectric layer having optional regions of a C-containing compound embedded therein.
Dependencies are inferred from the claim text.