Flash memory devices having self aligned shallow trench isolation structures

A flash memory device comprising:

• an integrated circuit substrate;
• a tunnel insulating pattern on a region of the integrated circuit substrate, wherein the tunnel insulating pattern has sidewalls;
• a floating gate pattern on the tunnel insulating pattern, wherein the floating gate pattern has sidewalls aligned to the sidewalls of the tunnel insulating pattern;
• a trench region aligned to the sidewalls of the floating gate pattern on the integrated circuit substrate adjacent to the tunnel insulating pattern;
• a trench oxide layer formed at a bottom of the trench region and sidewalls of the trench region at a predetermined depth from the tunnel insulating pattern of the trench region;
• and
• an insulating pattern aligned to the sidewalls of the floating gate pattern in the trench region and in contact with an upper sidewall of the trench region over the trench oxide layer, wherein a nitrogen doped layer is provided on the sidewalls of the floating gate pattern, the sidewalls of the tunnel insulating pattern and the upper sidewalls of the trench region.

A flash memory device comprising:

• an integrated circuit substrate;
• a tunnel insulating layer on the integrated circuit substrate;
• a floating gate pattern on the tunnel insulating layer, wherein the floating gate pattern has sidewalls;
• a control gate electrode formed on the intergate dielectric pattern, wherein the control gate electrode comprises sidewalls aligned to the sidewalls of the intergate dielectric pattern and the floating gate pattern;
• and
• a source/drain region aligned to the sidewalls of the floating gate pattern on the integrated circuit substrate adjacent to the floating gate pattern, wherein a nitrogen doped layer is provided on ones of the sidewalls of the floating gate pattern, the intergate dielectric pattern and the control gate electrode, which are sequentially aligned.

A flash memory device comprising:

• an integrated circuit substrate;
• a plurality of trench regions formed parallel to the integrated circuit substrate;
• a trench oxide layer at a bottom of the trench region and sidewalls thereof at a predetermined depth from a tunnel insulating pattern of the trench region;
• an insulating pattern in the trench region and in contact with an upper sidewall of the trench region over the trench oxide layer;
• a plurality of control gate electrodes crossing over the trench regions and parallel to each other;
• a plurality of floating gate patterns between the integrated circuit substrate and the control gate electrode, wherein the floating gate patterns have sidewalls aligned to the sidewalls of the insulating pattern;
• an intergate dielectric pattern between the control gate electrode and the floating gate patterns;
• and
• a tunnel insulating pattern between the floating gate pattern and the integrated circuit substrate, wherein the tunnel insulating pattern has sidewalls aligned to the sidewalls of the insulating pattern, and nitrogen doped layers are formed at each surface of the sidewalls of the tunnel insulating pattern, the floating gate pattern, and an upper sidewall of the trench region.