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US 2006/0151821 A1Published application
Memory device having trapezoidal bitlines and method of fabricating same
AssigneeSpansion LLC
InventorsAshot Melik-Martirosian, Mark Ramsbey, Mark Randolph
Life of this patent
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Abstract
A memory device and a method of fabrication are provided. The memory device includes a semiconductor substrate and a charge trapping dielectric stack disposed over the semiconductor substrate. A gate electrode is disposed over the charge trapping dielectric stack, where the gate electrode electrically defines a channel within a portion of the semiconductor substrate. The memory device includes a pair of bitlines, where the bitlines have a lower portion and a substantially trapezoidal shaped upper portion.
Claims29
A memory device comprising:
- a semiconductor substrate;
- a charge trapping dielectric stack disposed over the semiconductor substrate;
- a gate electrode disposed over the charge trapping dielectric stack, the gate electrode electrically defining a channel within a portion of the semiconductor substrate;
- and
- a pair of bitlines, the bitlines having a lower portion and a substantially trapezoidal shaped upper portion.
2 more elements
A method of fabricating a memory device comprising:
- providing a semiconductor substrate;
- forming a charge trapping dielectric stack over the semiconductor substrate;
- forming a gate electrode over the charge trapping dielectric stack;
- and
- forming a pair of bitlines on opposite sides of the charge trapping dielectric stack and gate electrode, the bitlines having a substantially trapezoidal upper portion.
2 more elements
Dependencies are inferred from the claim text.