Management of memory controller reset
AssigneeInternational Business Machines (IBM) Corporation
InventorsLucien Mirabeau, Charles Cardinell, Man Ma, Ricardo Padilla
Life of this patent
Estimating the term…
Abstract
An error handling method is provided for processing adapter errors. Rather than executing a disruptive controller hardware reset, an error handling routine provides instructions for a reset operation to be loaded and executed from cache while the SDRAM is in self-refresh mode and therefore unusable.
Claims18
A method for processing an error in an I/O adapter associated with a storage controller, comprising:
- receiving an adapter error in a memory controller to which a first memory device is coupled;
- quiescing processes requiring access to the first memory device;
- executing reset function code in a cache associated with the memory controller;
- initializing memory controller registers;
- and
- allowing processes to access the first memory device.
An adapter error handler, comprising:
- a processor;
- a memory controller coupled to the processor;
- a first memory device coupled to the memory controller;
- a second memory device coupled to the memory controller;
- a cache associated with the microprocessor coupled to the memory controller;
- and
- an error register associated with the memory controller adapted to store an indication of an error in an adapter coupled to the memory controller;
- the processor programmed to, upon receipt by the memory controller of the indication of an error in the adapter, execute instructions to:
- prevent external access to the first memory device;
- flush the cache;
- cause reset function code to execute in the cache, whereby registers associated with the memory controller are initialized;
- and
- permit external access to the first memory device.
A computer program product of a computer readable medium usable with a programmable computer, the computer program product having computer-readable code embodied therein for processing an error in an adapter associated with a storage controller, comprising, the computer-readable code comprising instructions for:
- receiving an adapter error in a memory controller to which is coupled a first memory device;
- quiescing processes requiring access to the first memory device;
- executing reset function code in a cache associated with the memory controller;
- initializing memory controller registers;
- and
- allowing processes to access the first memory device.
Dependencies are inferred from the claim text.