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US 2006/0141766 A1Published application
Method of manufacturing semiconductor device
AssigneeHynix Semiconductor Inc.
InventorJae Kim
Life of this patent
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Abstract
A method of manufacturing a semiconductor device in which an etching process for forming a M1 trench for a bit line is stopped on a nitride etch-stop film and the bit line is formed on the nitride film.
Claims16
A method of manufacturing a semiconductor device, comprising:
- (a) sequentially forming a first etch-stop film, a first interlayer insulating film, a second interlayer insulating film, a second etch-stop film, a buffer oxide film, and a first hard mask conductive film on a semiconductor substrate in which a first junction region is formed;
- (b) performing an etching process until the first etch-stop film is exposed to form a contact hole;
- (c) removing the exposed first etch-stop film to expose the first junction region;
- (d) forming the same conductive film as the first hard mask conductive film on the resulting surface, and performing a first planarization process to define a contact plug until the buffer oxide film is exposed;
- (e) sequentially forming a third interlayer insulating film, a second hard mask conductive film, and an anti-reflection film on the resulting surface including the contact plug;
- (f) patterning the anti-reflection film to define a region where a trench will be formed, and at the same time to form an anti-reflection film having a trapezoid shaped profile;
- (g) patterning the hard mask using the anti-reflection film having the trapezoid shaped profile as an etch mask;
- (h) performing an etching process until the second etch-stop film is exposed so that a trench is formed;
- and
- (i) forming the same conductive film as the second hard mask conductive film on the resulting surface, and performing a second planarization process to define a metal line until the third interlayer insulating film is exposed.
7 more elements
A method of forming a bit line of a NAND flash memory device, comprising:
- (a) sequentially forming a first etch-stop film, a first interlayer insulating film, a second interlayer insulating film, a second etch-stop film, a buffer oxide film, and a first hard mask conductive film on a semiconductor substrate in which a first junction region is formed;
- (b) performing an etching process until the first etch-stop film is exposed to form a contact hole;
- (c) removing the exposed first etch-stop film to expose the first junction region;
- (d) forming the same conductive film as the first hard mask conductive film on the resulting surface, and performing a first planarization process to define a contact plug until the buffer oxide film is exposed;
- (e) sequentially forming a third interlayer insulating film, a second hard mask conductive film, and an anti-reflection film on the resulting surface including the contact plug;
- (f) patterning the anti-reflection film to define a region where a trench will be formed, and at the same time to form an anti-reflection film having a trapezoid shaped profile;
- (g) patterning the hard mask using the anti-reflection film having the trapezoid shaped profile as an etch mask;
- (h) performing an etching process until the second etch-stop film is exposed so that a trench is formed;
- and
- (i) forming the same conductive film as the second hard mask conductive film on the resulting surface, and performing a second planarization process to define a bit line until the third interlayer insulating film is exposed.
7 more elements
Dependencies are inferred from the claim text.