US 2006/0141693 A1Published application

Semiconductor multilayer interconnection forming method

OwnerYoshio Hagiwara, Takeshi Tanakainventors

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Abstract

In a method for forming a wiring using a dual damascene process in which a multilayer wiring structure is formed by embedding a first etching space formed in an interlayer insulating layer and a second etching space which communicates thereto with a conductor material, a number of steps may be reduced and flexibility in the step management is enhanced without deteriorating a low dielectric material layer which constitutes the interlayer insulating layer. Therefor, a filler material whose major ingredient is a spin-on-glass material capable of being easily removed by a stripping solution which gives no damage to the interlayer insulating layer is used as a material filled in the first etching space in order to protect a lower wiring layer from exposure light to form a photoresist pattern for forming the second etching space. Furthermore, no light absorbing material for absorbing the exposure light is added to this filler material. Instead, a reflection preventing film capable of being processed by dry etching or a reflection preventing film which is soluble in a developer is formed on a filler material layer.

Claims15

Dependent claims

A method for forming a semiconductor multilayer wiring comprising a lower wiring layer formed on a semiconductor substrate and an upper wiring layer formed thereon by the intermediary of an interlayer insulating layer, said lower wiring layer and said upper wiring layer are connected by a via wiring which penetrates through said interlayer insulating layer, said method comprising:

a step of forming the interlayer insulating layer wherein said interlayer insulating layer composed of at least a low dielectric material layer is laminated on said lower wiring layer;
a step of forming a first etching space wherein the first etching space is formed in said interlayer insulating layer by forming a photoresist layer on said interlayer insulating layer, giving patterned exposure thereto, developing to form a photoresist pattern, and etching using this photoresist pattern as a mask;
a step of embedding wherein a filler material which at least contains a spin-on-glass material as a major ingredient is applied to said interlayer insulating layer, to embed said filler material in said first etching space;
a step of forming a reflection preventing film wherein the reflection preventing film capable of being processed by dry etching is formed on a filler material layer formed on said interlayer insulating layer;
a step of forming a photoresist pattern wherein the photoresist pattern is formed by forming a photoresist layer on said reflection preventing film, irradiating said photoresist layer with patterned light, and developing by an alkali developer;
a step of processing the reflection preventing film wherein an exposed part of said reflection preventing film is processed by dry etching using said photoresist pattern as a mask;
a step of forming a second etching space and removing the filler material wherein etching is performed using said photoresist pattern as a mask to remove said interlayer insulating layer above said first etching space in accordance with a predetermined pattern for forming the second etching space which communicates with said first etching space, and simultaneously to remove the filler material in said first etching space;
and
a step of simultaneous wiring formation wherein said first and second etching spaces are simultaneously embedded with a conductor material to simultaneously form a via wiring and an upper wiring layer.

6 more elements

a step of forming an interlayer insulating layer wherein said interlayer insulating layer composed of at least a low dielectric material layer is laminated on said lower wiring layer;
a step of forming a first etching space wherein the first etching space is formed in said interlayer insulating layer by forming a photoresist layer on said interlayer insulating layer, giving patterned exposure thereto, developing to form a photoresist pattern, and etching using this photoresist pattern as a mask;
a step of embedding wherein a filler material which at least contains a spin-on-glass material as a major ingredient is applied to said interlayer insulating layer, to embed said filler material in said first etching space;
a step of forming a reflection preventing film wherein a developer-soluble reflection preventing film is formed on a filler material layer formed on said interlayer insulating layer;
a step of forming a photoresist wherein a photoresist layer is formed on said developer-soluble reflection preventing film;
a step of developing the resist and removing the reflection preventing film wherein said photoresist layer is irradiated with patterned light and, with an alkali developer, the photoresist layer is developed, and simultaneously a part of the reflection preventing film that is not covered by the remaining photoresist pattern which has remained during the development is removed;
a step of forming a second etching space and removing the filler material wherein etching is performed using said photoresist pattern as a mask to remove said interlayer insulating layer above said first etching space in accordance with a predetermined pattern for forming the second etching space which communicates with said first etching space, and simultaneously to remove the filler material in said first etching space;
and
a step of simultaneous wiring formation wherein said first and second etching spaces are simultaneously embedded with a conductor material to simultaneously form a via wiring and an upper wiring layer.

6 more elements

Dependencies are inferred from the claim text.