Method and system for optimization of transistor sizing based on layout density

Abstract

A method (300) for generating an optical proximity correction model for a mask layout having an asymmetric feature structure includes fabricating a mask (310) having a plurality of symmetric and asymmetric test structures thereon, and image processing one or more semiconductor wafers (320) using the fabricated mask to create a plurality of symmetric and asymmetric resist structures overlying the one or more wafers. At least one critical dimension of the symmetric resist structures and the asymmetric resist structures are measured (330), thereby generating symmetric and asymmetric critical dimension data, and a difference between a desired feature size of the symmetric and asymmetric structures and the measured feature size of the symmetric and asymmetric structures is evaluated (380) in order to generate an optical proximity correction model (398) based thereon.

Dependencies are inferred from the claim text.