Input buffer circuit having a differential amplifier structure

An input buffer circuit having two differential input signals, the circuit comprising:

• a first P-channel transistor and a first N-channel transistor that are connected to each other at a first output node and connected in series between a current source node and a current sink node, and are commonly controlled by the first one of the two differential input signals;
• a second P-channel transistor and a second N-channel transistor that are connected in series between the current source node and the current sink node and are commonly controlled by the second one of the two differential input signals;
• a third P-channel transistor, configured to operate as a diode, connected between a power source voltage terminal and the first output node, and a third N-channel transistor, configured to operate as a diode, connected between the first output node and a ground terminal;
• and

An input buffer circuit having two input signals, the circuit comprising:

• a first P-channel transistor connected to a current source node and to a first output node;
• and a first N-channel transistor connected to the first output node and to a current sink node;
• the first P-channel transistor and the first N-channel transistor being commonly driven by a first input signal among the two input signals;
• a second P-channel transistor connected to the current source node and to a second node;
• and a second N-channel transistor connected to a third node and to the current sink node;
• the second P-channel transistor and the second N-channel transistor being commonly driven by the second input signal among the two input signals;
• a fourth P-channel transistor configured to operate as a diode connected between a power source voltage terminal and the second node;
• and a fourth N-channel transistor configured to operate as a diode connected between a third node and a ground terminal.

An input buffer circuit having two differential input signals, the circuit comprising:

• a current source connected between a power source voltage terminal and the current source node;
• a current sink connected between a current sink node and a ground terminal;
• a first P-channel transistor and a first N-channel transistor that are commonly driven by the first one of the two differential input signals, the first P-channel transistor being connected between the current source node and a first node, and the first N-channel transistor being connected between a second node and the current sink node;
• wherein a first output signal is output at the first node and a second output signal is output at the second node;
• a second P-channel transistor and a second N-channel transistor that are commonly driven by the second one of the two differential input signals, the second P-channel transistor being connected between the current source node and a third node, and the second N-channel transistor being connected between the current sink node and a fourth node;
• a first diode connected between a power source voltage terminal and the second node;
• and second diode connected between the first node and a ground terminal;
• a third diode connected between the power source voltage terminal and the third node;
• and a fourth diode connected between the fourth node and a ground terminal;
• and
• a fifth P-channel transistor and a fifth N-channel transistor, the fifth P-channel transistor being driven by the signal at the third node and being connected between a power source voltage terminal and the first node;
• and the fifth N-channel transistor being driven by the signal at the fourth node and being connected between the second node and a ground terminal.