Testing system and testing method for duts

A testing method for testing a first DUT, a second DUT, a third DUT, and a fourth DUT on a wafer, each of the first, second, third, and fourth DUTs comprising a first testing end and a second testing end, the testing method comprising:

• connecting the second testing ends of the first and fourth DUTs to a first conducting line;
• connecting the second testing ends of the second and third DUTs to a second conducting line;
• connecting the first testing ends of the first and second DUTs to a third conducting line;
• connecting the first testing ends of the third and fourth DUTs to a fourt conducting line;
• coupling a first testing pad to the first conducting line;
• coupling a second testing pad to the second conducting line;
• coupling a third testing pad to the third conducting line;
• coupling a fourth testing pad to the fourth conducting line;
• and
• utilizing the first, second, third, and fourth testing lads to receive at least one testing signal to detect device characteristics of the first, second, third, and fourth DUTs, and when the first and second testing Dads are utilized to transfer a first testing signal, floating the third and fourth testing pads.

A testing system for testing a plurality of DUTs (device under test) on a wafer, the plurality of DUTs arranged in an n*m matrix, each DUT having a row testing end and a column testing end, and the testing system comprising:

• n row testing pads each for receiving a testing signal, wherein n is not less than 2, a row testing pad of a first row is coupled to the row testing ends of the DUTs arranged on the first row, and a row testing pad of an nth row is coupled to the row testing ends of the DUTs arranged on the nth row;
• and
• m column testing pads each for receiving a testing signal, wherein m is not less than 2, a column testing pad of a first column is coupled to the column testing ends of the DUTs arranged on the first column, and a column testing pad of an mth column is coupled to the column testing ends of the DUTs arranged on the mth column;
• wherein the testing pads receive at least one testing signal to detect device characteristics of the plurality of DUTs, and when two specific row testing pads of the n row testing pads transfer a testing signal, the other testing pads are floating or when two column testing pads of the m column testing pads transfer a testing signal, the other testing pads are floating.

A testing method for testing a plurality of DUTs (device under test) on a wafer comprising:

• arranging the plurality of DUTs in an n*m matrix, wherein each DUT has a row testing end and a column testing end;
• providing n row testing pads, coupling a row testing pad of a first row to the row testing ends of the DUTs arranged on the first row, and coupling a row testing pad of an nth row to the row testing ends of the DUTs arranged on the nth row, wherein n is not less than 2;
• providing m column testing pads, coupling a testing pad of a first column to the column testing ends of the DUTs arranged on the first column, and coupling a testing pad of an mth column to the column testing ends of the DUTs arranged on the mth column, wherein m is not less than 2;
• utilizing the testing pads to receive at least one testing signal to detect device characteristics of the plurality of DUTs, and when utilizing two specific row testing pads of the n row testing pads to transfer a testing signal, floating the other testing pads, or when utilizing two column testing pads of the m column testing pads to transfer a testing signals floating the other testing pads.

A testing system for testing a first DUT (device under test), a second DUT, a third DUT, and a fourth DUT on a wafer, each of the first, second, third, and fourth DUTs comprising a first testing end and a second testing end, the testing system comprising:

• a testing circuit formed on the wafer comprising:
• a first conducting line connected to the second testing ends of the first and the fourth DUTs;
• a second conducting line connected to the second testing ends of the second and third DUTs;
• a third conducting line connected to the first testing ends of the first and second DUTs;
• a fourth conducting line connected to the first testing ends of the third and fourth DUTs;
• a plurality of testing pads respectively coupled to the first, second, third, and fourth conducting lines for receiving at least one testing signal to detect device characteristics of the first, second, third, and fourth DUTs;
• and
• a testing device, coupled to the testing pads, for detecting a plurality of electronic parameters corresponding to a plurality of sets of two different testing pads and comparing the electronic parameters to detect a specific device from the first, second, third, and fourth DUTs.

A testing method for testing a first DUT, a second DUT, a third DUT, and a fourth DUT on a wafer, each of the first, second, third, and fourth DUTs comprising a first testing end and a second end, the testing method comprising:

• connecting the second testing end of the first and fourth DUT to a first conducting line;
• connecting the second testing ends of the second and third DUTs to a second conducting line;
• connecting the first end of the first and second DUTs to a third conducting line;
• connecting the first end of the third and fourth DUTs to a fourth conducting line;
• providing a plurality of testing pads respectively coupled to the first, second, third, and fourth conducting lines;
• and
• detecting a plurality of electronic parameters corresponding to a plurality of sets of two different testing pads and comparing the electronic parameters to detect a specific device from the first, second, third, and fourth DUTs.

A testing system for testing a plurality of DUTs (device under test) on a wafer, the plurality of DUTs arranged in an n*m matrix, each DUT having a row testing end and a column testing end, and the testing system comprising:

• n row testing pads for receiving a testing signal, wherein n is not less than 2, a row testing pad of the first row is coupled to the row testing ends of the DUTs arranged on the first row, and a row testing pad of the nth row is coupled to the row testing ends of the DUTs arranged on the nth row;
• and
• m column testing pads for receiving a testing signal, wherein m is not less than 2, a column testing pad of the first column is coupled to the column testing ends of the DUTs arranged on the first column, and a column testing pad of the mth column is coupled to the column testing ends of the DUTs arranged on the mth column;
• and
• a testing device, coupled to the n row testing pads and the m column testing pads, for detecting a plurality of electronic parameters corresponding to a plurality of sets of two different testing pads and comparing the electronic parameters to detect a specific device from the DUTs.

A testing method for testing a plurality of DUTs (device under test) on a wafer comprising:

• arranging the plurality of DUTs in an n*m matrix, wherein each DUT has a row testing end and a column testing end;
• providing n row testing pads, coupling a row testing pad of the first row to the row testing ends of the DUTs arranged on the first row, and coupling a row testing pad of the nth row is coupled to the row testing ends of the DUTs arranged on the nth row, wherein m is not less than 2;
• and
• providing m column testing pads, coupling a testing pad of the first column to the column testing ends of the DUTs arranged on the first column, and coupling a testing pad of the mth column is coupled to the column testing ends of the DUTs arranged on the mth column, wherein m is not less than 2;
• and
• detecting a plurality of electronic parameters corresponding to a plurality of sets of two different testing pads and comparing the electronic parameters to detect a specific device from the DUTs.