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US 2006/0138593 A1Published application
Capacitor of semiconductor device and manufacturing method thereof
AssigneeDongbuAnam Semiconductor Inc.
InventorMin Kim
Life of this patent
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Abstract
In a capacitor of a semiconductor device, a bottom electrode is formed on a substrate and has an uneven top surface. An interlayer insulation layer is formed on the substrate and has a via hole exposing the top surface of the bottom electrode. A dielectric layer is formed unevenly on the bottom electrode. A top electrode is formed on the dielectric layer while filling the via hole.
Claims20
A capacitor of a semiconductor device, comprising:
- a bottom electrode formed on a substrate, the bottom electrode having an uneven top surface;
- an interlayer insulation layer formed on the substrate, the interlayer insulation layer having a via hole exposing the top surface of the bottom electrode;
- a dielectric layer formed unevenly on the bottom electrode;
- and
- a top electrode formed on the dielectric layer while filling the via hole.
2 more elements
A method of manufacturing a capacitor of a semiconductor device, comprising:
- forming a first conductive layer on a substrate;
- selectively etching the first conductive layer to form a first interconnection and a bottom electrode with an uneven top surface;
- forming an interlayer insulation layer on the substrate where the first interconnection and the bottom electrode are formed;
- selectively etching the interlayer insulation layer to form a first via hole exposing a surface of the bottom electrode, and forming a dielectric layer on the bottom electrode;
- selectively etching the interlayer insulation layer to form a second via hole exposing a top surface of the first interconnection, and forming a conductive plug and a via plug in the first via hole and the second via hole, respectively;
- forming a second conductive layer on the interlayer insulation layer wherein the conductive plug and the via plug are formed;
- and
- selectively etching the second conductive layer to form a second interconnection connecting to the via plug and a conductive layer connecting to the conductive plug.
5 more elements
A method of manufacturing a capacitor of a semiconductor device, comprising:
- forming a first conductive layer on a substrate;
- patterning and etching the first conductive layer to form a first interconnection and a bottom electrode;
- forming an interlayer insulation layer on the substrate where the first interconnection and the bottom electrode are formed;
- etching the interlayer insulation layer to form a first via hole exposing a predetermined portion of a surface of the bottom electrode;
- forming unevenness on a top surface of the bottom electrode;
- forming a dielectric layer on the bottom electrode;
- selectively etching the interlayer insulation layer to form a second via hole exposing a top surface of the first interconnection, and forming a conductive plug and a via plug in the first via hole and the second via hole, respectively;
- forming a second conductive layer on the interlayer insulation layer where the conductive plug and the via plug are formed;
- and
- selectively etching the second conductive layer to form a second interconnection connecting to the via hole and a conductive layer connecting to the conductive plug.
7 more elements
Dependencies are inferred from the claim text.