Flash memories having at least one resistance pattern on gate pattern and methods of fabricating the same

A semiconductor device comprising:

• gate patterns disposed in a first region and a second region of a semiconductor substrate;
• bit line patterns disposed in the first and second regions and disposed on the gate patterns;
• at least one resistance pattern disposed in the second region and disposed on one of the bit line patterns;
• and
• interconnection lines disposed in the first region and in the second region, one of the interconnection lines arranged on the at least one resistance pattern and in electrical contact with the resistance pattern.

A method of fabricating a flash memory comprising:

• forming gate patterns that are disposed in a first region and in a second region of a semiconductor substrate;
• forming bit line patterns on the gate patterns;
• covering the bit line patterns with a bit line interlayer insulating layer;
• forming at least one resistance pattern on the bit line interlayer insulating layer in the first region;
• covering the resistance pattern and the bit line interlayer insulating layer with a planarized interlayer insulating layer;
• and
• forming interconnection lines on the planarized interlayer insulating layer in the first and second regions of the semiconductor substrate, the interconnection lines and the bit line patterns crossing over the semiconductor substrate in the first region of the semiconductor substrate in substantially the same direction, one of the interconnection lines in electrical contact with the at least one resistance pattern.

A method of fabricating a semiconductor device comprising:

• forming gate patterns that are disposed in a first region and a second region of a semiconductor substrate;
• forming bit line patterns on the gate patterns in the first region and the second region;
• covering the bit line patterns with a bit line interlayer insulation layer;
• forming at least one resistance pattern on the bit line interlayer insulating layer in the second region;
• covering the bit line interlayer insulating layer and the resistance pattern with a planarized interlayer insulating layer;
• and
• electrically connecting a interconnection line to the at least one resistance pattern, the interconnection line one of a plurality of interconnection lines formed on the planarized interlayer insulating layer in the first region and in the second region.