ESD protection structure for I/O pad subject to both positive and negative voltages
AssigneeActel Corporation, a California Corporation
InventorGregory Bakker
Life of this patent
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Abstract
An ESD protection circuit is disclosed for an n-channel MOS transistor formed in an inner p-well of a triple-well process and connected to an I/O pad that may experience both positive and negative voltages according to the present invention. A first switch connects the p-well containing the n-channel MOS transistor to ground if the voltage at the I/O pad is positive and a second switch connects the p-well containing the n-channel MOS transistor to the I/O pad if the voltage at the I/O pad is negative. A third switch connects the gate of the n-channel MOS transistor to the p-well if it is turned off and a fourth switch connects the gate of the n-channel MOS transistor to VCC if it is turned on.
Claims17
An ESD protection circuit for an n-channel MOS transistor formed in an inner p-well of a triple-well structure and connected to an I/O pad that may experience both positive and negative voltages comprising:
- a first semiconductor switch connecting the p-well containing the n-channel MOS transistor to ground if the voltage at the I/O pad is positive;
- a second semiconductor switch connecting the p-well containing the n-channel MOS transistor to the I/O pad if the voltage at the I/O pad is negative;
- a third semiconductor switch connecting the gate of the n-channel MOS transistor to the p-well if the n-channel MOS transistor is turned off;
- and
- a fourth semiconductor switch connecting the gate of the n-channel MOS transistor to VCC if the n-channel MOS transistor is turned on.
An ESD protection circuit for an n-channel MOS transistor formed in an inner p-well of a triple-well structure and connected to an I/O pad that may experience both positive and negative voltages comprising:
- a first semiconductor switch connecting the p-well containing the n-channel MOS transistor to ground if the voltage at the I/O pad is positive;
- a second semiconductor switch connecting the p-well containing the n-channel MOS transistor to the I/O pad if the voltage at the I/O pad is negative;
- a resistor coupled between the gate of the n-channel MOS transistor and the p-well containing the n-channel MOS transistor;
- and
- a third semiconductor switch connecting the gate of the n-channel MOS transistor to VCC to turn the n-channel MOS transistor on.
A method for protecting structures coupled to an I/O pad of an integrated circuit including a triple-well structure having an inner p-well containing an n-channel MOS transistor having a drain coupled to the I/O pad, including:
- sensing the polarity of an external potential applied to the I/O pad;
- coupling the inner p-well to ground if the external potential applied to the I/O pad is positive;
- and
- coupling the inner p-well to the I/O pad if the external potential applied to the I/O pad is negative.
An ESD protection circuit for an n-channel MOS transistor formed in an inner p-well of a triple-well structure and connected to an I/O pad that may experience both positive and negative voltages comprising:
- a first semiconductor switch connecting the p-well containing the n-channel MOS transistor to ground if the voltage at the I/O pad is positive;
- and
- a second semiconductor switch connecting the p-well containing the n-channel MOS transistor to the I/O pad if the voltage at the I/O pad is negative.
Dependencies are inferred from the claim text.