Flash memory devices comprising pillar patterns and methods of fabricating the same

A NAND flash memory device, comprising:

• an isolation layer formed in a semiconductor substrate and defining a plurality of parallel active regions;
• a string select line and a ground select line crossing over the active regions;
• a plurality of floating gates arranged between the string select line and the ground select line, disposed above the active regions, and having widths which are larger than widths of the active regions;
• pillar patterns having sidewalls and bottom surfaces covered by the isolation layer, and disposed lower than bottom surfaces of the floating gates;
• and
• a plurality of control gate electrodes overlapping the floating gates and crossing over the active regions,
• wherein each of the control gate electrodes includes control gate extensions which penetrate between the floating gates and are formed above the pillar patterns.

A method of fabricating a flash memory device, comprising:

• forming a plurality of parallel trench mask patterns on a semiconductor substrate;
• etching the semiconductor substrate using the trench mask patterns as etch masks to form a trench region defining a plurality of parallel active regions;
• forming an isolation layer and a pillar filling the trench region, wherein sidewalls and a bottom surface of the pillar are covered by the isolation layer;
• removing the trench mask patterns to form grooves exposing the active regions;
• forming insulated floating gate patterns filling the grooves;
• selectively etching the pillar to form recessed regions between the floating gate patterns;
• sequentially forming an inter-gate dielectric layer and a control gate conductive layer on the semiconductor substrate having the recessed regions;
• and
• continuously patterning the control gate conductive layer, the inter-gate dielectric layer, and the floating gate patterns to form floating gates interposed between control gate electrodes and the active regions as well as the plurality of control gate electrodes crossing over the active regions,
• wherein each of the control gate electrodes has control gate extensions which penetrate between the floating gates.