Ferroelectric memory

A ferroelectric memory, comprising:

• a first N channel MOS transistor connected between N1 and N2 nodes;
• a second N channel MOS transistor connected between the N2 node and an N3 node;
• a first P channel MOS transistor connected between P1 and P2 nodes;
• a second P channel MOS transistor connected between the P2 node and a P3 node;
• a first wiring formed in a first wiring layer to interconnect the N1 node and the Pi node;
• a second wiring formed in the first wiring layer to interconnect the N3 node and the P3 node;
• a third wiring formed in a second wiring layer different from the first wiring layer to interconnect the N2 node and the P2 node;
• a first ferroelectric capacitor whose first electrode is connected to the first wiring;
• and
• a second ferroelectric capacitor whose first electrode is connected to the second wiring,
• wherein a second electrode of the first ferroelectric capacitor is connected to the P2 node or the N2 node, and a second electrode of the second ferroelectric capacitor is connected to the N2 node or the P2 node.

A ferroelectric memory, comprising:

• a first N channel MOS transistor connected between N1 and N2 nodes;
• a second N channel MOS transistor connected between the N2 node and an N3 node;
• a first P channel MOS transistor connected between P1 and P2 nodes;
• a second P channel MOS transistor connected between the P2 node and a P3 node;
• a first wiring formed in a first wiring layer to interconnect the N2 node and the P2 node;
• a second wiring formed in a second wiring layer different from the first wiring layer to interconnect the N1 node and the P1 node;
• a third wiring formed in the second wiring layer to interconnect the N3 node and the P3 node;
• and
• first and second ferroelectric capacitors whose first electrodes are connected to the first wiring,
• wherein a second electrode of the first ferroelectric capacitor is connected to the P1 node or the N1 node, and a second electrode of the second ferroelectric capacitor is connected to the N3 node or the P3 node.

A ferroelectric memory, comprising:

• a first N channel MOS transistor connected between N1 and N2 nodes;
• a second N channel MOS transistor connected between the N2 node and an N3 node;
• a first P channel MOS transistor connected between P1 and P2 nodes;
• a second P channel MOS transistor connected between the P2 node and a P3 node;
• a first wiring formed in a first wiring layer to interconnect the N1 node and the P1 node;
• a second wiring formed in the first wiring layer to interconnect the N3 node and the P3 node;
• a first ferroelectric capacitor whose first electrode is connected to the first wiring;
• and
• a second ferroelectric capacitor whose first electrode is connected to the second wiring,
• wherein second electrodes of the first and second ferroelectric capacitors are integrated as one electrode, and the one electrode is connected to the N2 node or the P2 node.