US 2006/0138411 A1 · Semiconductor wafer with a test structure, and method

Abstract

The invention proposes a semiconductor wafer with a test structure for detecting parasitic contact structures on the semiconductor wafer, in which a first interconnect plane (A) contains interconnects (1) running parallel to one another and a second interconnect (2) that is arranged between the latter. The two first interconnects (1) are connected by means of contact elements (4) arranged above them, to a third interconnect (3) that runs in a second interconnect plane (B) transverse to the first and second interconnects, and that also crosses the second interconnect (2). If there is a parasitic contact structure (5) formed between the contact elements (4), which has arisen during the lithographic exposure for producing the contact elements (4) on account of constructively interfering diffraction maxima, then this shorts the second interconnect (2) to the third interconnect (3). This results in a leakage current path perpendicular to the substrate surface (10a), the path extending from the second (2) to the third (3) interconnect even in the case of very narrow parasitic contact structures (5). When test needles are placed in contact with the second and third interconnects, an electrical measurement allows the extent of a parasitic contact structure (5) to be detected with a particularly high level of probability.

Claims25

Dependent claims

A semiconductor wafer with a test structure, the semiconductor wafer comprising:

a substrate;
at least two first interconnects that are arranged in a first interconnect plane over the substrate and that include sections that run substantially parallel to one another at least in sections;
at least one second interconnect that is arranged in the first interconnect plane between the sections of the two first interconnects, the at least one second interconnect running substantially parallel to the sections of the first interconnects;
a third interconnect that runs in a second interconnect plane over the substrate, the second interconnect plane being arranged at a greater distance from a surface of the substrate than the first interconnect plane;
and
at least one respective contact element on each of the two first interconnects, the contact element electrically connecting the respective first interconnect to the third interconnect, wherein the distance between the second interconnect and the two first interconnects corresponds to the lithographic resolution limit of the first interconnect plane;
and
wherein the contact elements are arranged at positions being mirror-inverted with respect to one another in relation to the second interconnect running between the first interconnects.

5 more elements

A method for detecting parasitic contact structures on a semiconductor wafer with a test structure, the method comprising:

providing a test structure comprising:
at least two first interconnects that are arranged in a first interconnect plane, at least interconnect sections of the two first interconnects running parallel to one another;
at least one second interconnect that is arranged in the first interconnect plane between the two first interconnects and that runs parallel to the interconnect sections of the first interconnects;
a third interconnect that runs in a second interconnect plane that is arranged at a greater distance from a surface of the semiconductor wafer than the first interconnect plane;
and
at least one respective contact element on each of the two first interconnects the contact element electrically conductively connecting the respective first interconnect to the third interconnect;
wherein the method comprises:
connecting the second interconnect to a first electrical potential and connecting the third interconnect to a different, second electrical potential;
and
performing an electrical resistance or current measurement, thereby measuring whether the third interconnect is conductively connected to the second interconnect.

7 more elements

Dependencies are inferred from the claim text.

Semiconductor wafer with a test structure, and method

Life of this patent

Semiconductor wafer with a test structure, and method

Life of this patent

Abstract

Claims25