Layout modification using multilayer-based constraints

A computer readable medium including instructions executable by a computer, wherein the instructions perform a method for improving manufacturability of a semiconductor device layout design comprising:

• performing at least one of width, space and area checks on more than one of multiple interacting layers of a design;
• and
• modifying the design in response to results of the at least one of width, space and area checks, wherein modifying the design includes moving predetermined feature edges in an altered design database to decrease a risk of at least one of feature widths, feature spaces, and feature enclosures being patterned smaller than designed.

A method for improving manufacturability of a semiconductor device layout design comprising:

• performing at least one interlayer space check and one intralayer space check on more than one of multiple interacting layers of a design;
• and
• modifying at least one of a contact, via or implant target design layers of the target design in response to results of the at least one of the space checks to create an altered target design database, wherein modifying the design includes moving at least one or more predetermined edges of a feature on the at least one of the contact, via or implant target design layers in order to decrease a risk of at least one of feature widths, feature spaces, feature electrical conductivity and feature enclosures being manufactured smaller than designed.