Cell, standard cell, standard cell library, a placement method using standard cell, and a semiconductor integrated circuit

A standard cell library for synthesizing a functional macro layout, wherein a standard cell having a cell width different to a dimension corresponding to an integral multiple of a routing grid interval is included.

A standard cell placement method as a design method for synthesizing a functional macro layout using a standard cell, wherein

• a Y coordinate of a cell origin of at least a standard cell is located at a midpoint between adjacent routing grids or on the routing grid in automatic placement & routing, and
• an X coordinate of the cell origin of the standard cell is located at the midpoint between the adjacent routing grids or at a position not on the routing grid.

A standard cell placement method as a design method for synthesizing a functional macro layout using a standard cell, wherein

• the standard cell is tentatively placed, and when a Y coordinate of a cell origin of the standard cell tentatively placed is located at a midpoint between adjacent routing grids or on the routing grid in automatic placement & routing and an X coordinate of the cell origin of the standard cell is located at the midpoint between the adjacent routing grids or on the routing grid, the cell origin is shifted to a position at which the standard cell having the cell origin is in contact with a standard cell adjacent thereto.

A standard cell placement method as a design method for synthesizing a functional macro layout using a standard cell, wherein

• the standard cell is tentatively placed, and
• when the standard cell tentatively placed includes a first group of cells each having a cell width corresponding to an integral multiple of a routing grid interval in automatic placement & routing, the first group of cells is replaced with a second group of cells each having a cell width not necessarily corresponding to the integral multiple of the routing grid interval.

A standard cell comprising a plurality of gate electrodes, wherein

• a cell width of the standard cell along an X direction in parallel with a power-supply wiring of the standard cell is an integral multiple of a numeral value different to a routing grid interval along the X direction.

A standard cell comprising a plurality of gate electrodes, wherein

• gate pitches of some of the gate electrodes are set to values different to the routing grid interval set along an X direction in parallel with a power-supply wiring of the standard cell, and
• a cell width along the X direction in parallel with the power-supply wiring of the standard cell is set to an integral multiple of a minimum value of the gate pitches of the gate electrodes set to the values different to the routing grid interval set along the X direction.

A standard cell placement method as a design method for synthesizing a functional macro layout using a standard cell, wherein

• a Y coordinate of a cell origin of at least a standard cell is located at a midpoint between adjacent routing grids or on the routing grid in automatic placement & routing, and
• an X coordinate of the cell origin of the standard cell is located at the midpoint between gate pitch grids different to the adjacent routing grids or on the gate pitch grid.