Test method, control circuit and system for reduced time combined write window and retention testing

A test mode control circuit comprising:

• a. a main control circuit that receives as input trigger sequence signals and generates as output wordline activation control signals and bitline control signals to achieve a desired timing sequence for a combined write window and retention test of a memory device;
• b. a wordline control circuit coupled to the main control circuit and responsive to the wordline activation control signals to generate wordline activation signals and wordline deactivation signals that are supplied to wordlines associated with storage cells in the memory device;
• and
• c. a sense amplifier control circuit coupled to the main control circuit and responsive to the bitline control signals to control the bitlines associated with the storage cells in the memory device.

A method of performing a combined write window test and a retention test of a memory device, comprising:

• a. controlling time intervals during which wordlines are activated and deactivated and bitlines are grounded or connected to a bitline high voltage such that the wordlines are activated while bitlines are either grounded or at the bitline high voltage;
• b. during a first time interval after the wordlines are activated writing a first value to storage cells associated with the activated wordlines;
• c. during a second time interval after a second activation of the wordlines writing a second value to storage cells associated with activated wordlines, wherein the second time interval has a duration that establishes write window test conditions;
• d. after expiration of a third time interval corresponding to a retention time interval, reading the storage cells;
• and
• e. determining whether a storage cell has passed or failed a combined write window and retention test based on a value read from the storage cell.

A test mode control circuit comprising:

• a. main controlling means responsive to input trigger sequence signals for generating as output wordline activation control signals and bitline control signals to achieve a desired timing sequence for a combined write window and retention test of a memory device;
• b. wordline controlling means coupled to the main controlling means and responsive to the wordline activation control signals for generating wordline activation signals and wordline deactivation signals that are supplied to wordlines associated with storage cells in the memory device;
• and
• c. sense amplifier controlling means coupled to the main controlling means and responsive to the bitline control signals to control the bitlines associated with the storage cells in the memory device.