Method of forming a metal interconnection line in a semiconductor device using an FSG layer

Abstract

A method of forming a metal line in a semiconductor device using a fluorine doped silica glass (FSG) insulation layer. The method includes forming a lower metal layer on a insulation layer on a semiconductor substrate, forming a metal oxide layer on a sidewall of the lower metal layer, forming a barrier insulation layer covering the lower metal layer and metal oxide layer, forming an FSG insulation layer on the barrier insulation layer, forming a via contact that penetrates the FSG insulation layer so as to connect to the lower metal layer, and forming an upper metal layer electrically connected to the via contact.

Dependencies are inferred from the claim text.