Method to improve device isolation via fabrication of deeper shallow trench isolation regions

A method of forming a shallow trench isolation (STI) structure in a semiconductor substrate wherein the depth of said STI structure is greater than the depth of a shallow trench shape defined in said semiconductor substrate, comprising the steps of:

• forming a first silicon oxide layer;
• forming a silicon nitride layer;
• performing a first dry etch procedure using a photoresist shape as an etch mask, to form an opening in said silicon nitride and said first silicon oxide layer;
• performing a second dry etch procedure using said photoresist shape as an etch mask, to define said shallow trench shape featuring tapered sides in a top portion of said semiconductor substrate;
• using said photoresist shape as a mask performing an ion implantation procedure to place oxygen ions into portions of said semiconductor substrate exposed at bottom of said shallow trench shape and into tapered sides of said semiconductor substrate exposed in said shallow trench shape;
• growing a silicon oxide liner layer on surfaces of said semiconductor substrate exposed in said shallow trench shape;
• performing an anneal procedure to activate said oxygen ions forming a silicon oxide region in portions of said semiconductor substrate exposed at bottom of, and on tapered sides of said shallow trench shape;
• depositing a second silicon oxide layer completely filling said shallow trench shape;
• selectively removing portions of said second silicon oxide from tp surface of said silicon nitride layer;
• and
• selectively removing said silicon nitride layer.

A shallow trench isolation (STI) structure in a semiconductor substrate, comprising:

• an shallow trench shape with tapered sides, located in a top portion of said semiconductor substrate;
• a silicon oxide liner layer located on tapered sides and on bottom of said shallow trench shape;
• a silicon oxide shape featuring a first portion of said first silicon oxide shape located entirely in said shallow trench shape interfacing underlying said silicon oxide liner layer, and featuring a second portion of said silicon oxide shape located overlying said first silicon oxide shape;
• and
• a silicon oxide region featuring a first portion of said silicon region located directly below bottom of said first portion of said silicon oxide shape, and a second portion of said silicon oxide region interfacing portions of said silicon oxide liner layer located on tapered sides of said shallow trench shapes, with thickness of said second portion of said silicon oxide region decreasing with decreasing depth of said shallow trench shape, resulting in a silicon oxide region comprised with straight sides.