Method for fabricating a buried conductive connection to a trench capacitor and a memory cell with such a connection

A method for fabricating a memory cell in a semiconductor substrate, having

• a trench capacitor having an inner capacitor electrode provided in a trench, the inner capacitor electrode in a lower trench region being isolated from an outer capacitor electrode which is formed around the lower trench region, by a dielectric intermediate layer, the inner capacitor electrode in an upper trench region being isolated from the semiconductor substrate essentially by an insulator layer on the trench sidewall, and the inner capacitor electrode in the upper trench region having a conductive material layer containing a dopant, which material layer has a contact area with the semiconductor substrate between a first and a second predetermined trench depth,
• and a selection transistor having a first electrode region adjoining the trench capacitor, a channel region isolated from a gate electrode by an insulator layer, and a second electrode region,
• the first electrode region of the selection transistor being connected to the inner capacitor electrode of the trench capacitor via a buried connection, which is formed by outdiffusing dopant from the conductive material layer containing the dopant into the semiconductor substrate in the region of the contact area, in order to form a buried conductive connection in the semiconductor substrate, by etching back the conductive material layer containing the dopant into the trench as far as a third trench depth lying between the first and second predetermined trench depths, and by covering the trench with an insulator layer.

A method for fabricating a memory cell in a semiconductor substrate, having the steps of:

• forming a trench capacitor in the semiconductor substrate having an inner capacitor electrode provided in a trench, the inner capacitor electrode in a lower trench region being isolated from an outer capacitor electrode which is formed around the lower trench region, by a dielectric intermediate layer, the inner capacitor electrode in an upper trench region being isolated from the semiconductor substrate essentially by an insulator layer on the trench wall, and the inner capacitor electrode in the upper trench region having a conductive material layer containing a dopant, which material layer has a contact window with the semiconductor substrate between a first and a second predetermined trench depth,
• forming a buried conductive connection in the semiconductor substrate by indiffusing dopant from the conductive material layer containing the dopant into the semiconductor substrate via the contact window,
• etching back the conductive material layer containing the dopant into the trench as far as a third trench depth lying between the first and second predetermined trench depths, in order to define a contact area between the inner capacitor electrode and the buried conductive connection formed by outdiffusion,
• covering the trench with an insulator layer, and
• forming a selection transistor having a first electrode region adjoining the trench capacitor, a channel region isolated from a gate electrode by an insulator layer, and a second electrode region, the first electrode region of the selection transistor being connected to the inner capacitor electrode of the trench capacitor via a buried conductive connection.