Multi-thickness dielectric for semiconductor memory
AssigneeSanDisk Corporation
InventorsMasaaki Higashitani, Tuan Pham
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Abstract
A process provides a gate dielectric layer of a first thickness for a memory array and for certain peripheral circuits on the same substrate as the memory array. High-voltage peripheral circuits are provided with a gate dielectric layer of a second thickness. Low-voltage peripheral circuits are provided with a gate dielectric layer of a third thickness. The process provides protection from subsequent process steps for a gate dielectric layer. Shallow trench isolation allows the memory array cells to be extremely small, thus providing high storage density.
Claims19
A method of forming a non-volatile memory array and array circuits on a surface of a substrate, the array circuits including a high-voltage region and a low-voltage region, the non-volatile memory array having shallow trench isolation structures, comprising:
- forming a first silicon dioxide layer of a first thickness that covers a first plurality of portions of the surface;
- subsequently forming a second silicon dioxide layer of a second thickness across the surface of the substrate including a second plurality of portions of the surface, the second thickness being less than the first thickness;
- forming a first polysilicon layer over the second silicon dioxide layer;
- removing a plurality of portions of the first polysilicon layer and the second silicon dioxide layer to expose a third plurality of portions of the surface;
- forming a third silicon dioxide layer over the third plurality of portions of the surface;
- and
- subsequently forming the shallow trench isolation structures in the surface.
A method of forming a memory system on the surface of a substrate that includes a memory array portion and a periphery having a high-voltage portion, mid-voltage portion and a low-voltage portion, comprising:
- forming a memory array dielectric layer of a first thickness overlying the memory array portion and the mid-voltage portion;
- forming a floating gate layer overlying the memory array dielectric layer;
- forming a high-voltage dielectric layer of a second thickness overlying the high-voltage portion;
- forming a low-voltage dielectric layer of a third thickness overlying the low-voltage portion;
- and
- subsequently forming a plurality of shallow trench isolation structures that divide the floating gate layer into separate portions.
A memory system that stores data in a memory array having peripheral circuits including a high-voltage circuit and a low-voltage circuit, comprising:
- a memory array having a plurality of floating gates that are self-aligned to shallow trench isolation structures and having a gate dielectric of a first thickness underlying the plurality of floating gates;
- a high-voltage circuit having a gate dielectric of a second thickness;
- a mid-voltage circuit having a gate dielectric of the first thickness;
- and
- a low-voltage circuit having a gate dielectric of a third thickness.
Dependencies are inferred from the claim text.