Memory device and fabrication thereof
AssigneeNanya Technology Corporation
InventorCheng-Chih Huang
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Abstract
A semiconductor memory device. A trench capacitor disposed at a lower portion of a trench in a substrate, in which the trench capacitor comprises a filling electrode layer and a collar dielectric layer surrounding the filling electrode layer. The top of the collar dielectric layer is lower than top surface level of the filling electrode layer. A vertical transistor is disposed at the upper portion of the trench, comprising a doped region disposed in a portion of the trench adjacent to the trench. A buried conductive layer interposed between the vertical transistor and the trench capacitor, wherein the cross section of the buried conductive layer is H shaped. The trench capacitor and the doping region of vertical transistor are electrically connected through the H shaped buried conductive layer.
Claims20
A method for forming a memory device, comprising:
- providing a substrate comprising a trench, wherein a trench capacitor is disposed in a lower portion of the trench, the trench capacitor comprises a filling electrode layer and a collar dielectric layer surrounding the filling electrode layer, top of the collar dielectric layer is lower than the top surface level the filling electrode layer;
- conformally forming a barrier layer overlying the collar dielectric layer, the filling electrode layer and sidewalls of the trench;
- conformally depositing a conductive layer overlying the barrier layer;
- forming a buried strap definition layer on the conductive layer over the filling electrode layer;
- and
- removing a portion of the conductive layer over the buried strap definition layer using the buried strap definition layer as an etching stop.
A semiconductor memory device, comprises:
- a substrate, comprising a trench;
- a trench capacitor disposed at lower portion of the trench, comprises a filling electrode layer and a collar dielectric layer surrounding the filling electrode layer, wherein top of the collar dielectric layer is lower than top surface level of the filling electrode layer;
- a vertical transistor disposed at upper portion of the trench, wherein the vertical transistor comprises a doped region disposed in a portion of the trench adjacent to the trench;
- a buried conductive layer interposed between the vertical transistor and the trench capacitor, wherein the cross section of the buried conductive layer is H shaped;
- and
- wherein the trench capacitor and the doping region of vertical transistor are electrically connected through the H shaped buried conductive layer.
Dependencies are inferred from the claim text.