Standard cell back bias architecture
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChing-Hao Shaw, Chih Wu, Charlie Chueh
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Abstract
An apparatus including, in one embodiment, a CMOS device cell including at least first and second CMOS transistors having first and second CMOS transistor doped regions in first and second doped wells, respectively, wherein each of the first and second CMOS transistor doped regions is configured to be biased with a corresponding one of a power supply potential and a ground potential. Such an embodiment also includes a tap cell having first and second tap cell doped regions in the first and second doped wells, respectively, wherein each of the first and second tap cell doped regions is configured to be biased with a different potential relative to the power supply and ground potential.
Claims20
A method for use in manufacturing a CMOS device cell, comprising:
- forming a first CMOS transistor in a first CMOS transistor doped region that is located in a first doped well of the CMOS device cell, wherein the first CMOS transistor doped region is configured to be biased with a power supply potential;
- forming a second CMOS transistor in a second CMOS transistor doped region that is located in a second doped well of the CMOS device cell, wherein the second CMOS transistor doped region is configured to be biased with a ground potential;
- forming a first tap cell doped region in the first doped well;
- and
- forming a second tap cell doped region in the second doped well, wherein each of the first and second tap cell doped regions is configured to be biased with a potential that is different relative to each of the power supply and ground potentials.
A method for use in manufacturing a CMOS device, comprising:
- forming a plurality of tap cells and a plurality of CMOS transistor devices, wherein:
- each of the tap cells is associated with at least one of the CMOS transistor devices,
- ones of the CMOS transistor devices are configured to be biased with one of a power supply potential and a ground potential, and
- each of the tap cells is configured to back-bias associated ones of the CMOS transistor devices with one of first and second potentials that are each a different potential relative to the power supply and ground potentials.
A method for use in manufacturing a CMOS device, comprising:
- forming a first well in a substrate, the first well having a first dopant type and a first dopant concentration;
- forming a second well in the substrate proximate the first well, the second well having a second dopant type and a second dopant concentration, wherein the first and second dopant types are different;
- forming a first doped region of a tap cell in the first well, the first doped region having the first dopant type and a third dopant concentration, wherein the third dopant concentration is substantially greater than the first dopant concentration;
- forming a second doped region of the tap cell in the second well, the second doped region having the second dopant type and a fourth dopant concentration, wherein the fourth dopant concentration is substantially greater than the second dopant concentration;
- forming a plurality of CMOS device cells each including a plurality of CMOS transistor devices each having source/drain regions in a corresponding one of the first and second wells;
- forming power supply and ground interconnects collectively connecting the source/drain regions of ones of the plurality of CMOS transistor devices at least indirectly to a corresponding one of a power supply and ground to bias the connected source/drain regions with a corresponding one of a power supply potential and a ground potential;
- and
- forming a first back-bias interconnect and a second back-bias interconnect collectively connecting the first and second wells at least indirectly to first and second back-bias sources, respectively, to bias the first and second wells with first and second back-bias potentials, respectively, that are each a different potential relative to the power supply and ground potentials.
Dependencies are inferred from the claim text.