Low-voltage, multiple thin-gate oxide and low-resistance gate electrode
AssigneeSanDisk Corporation
InventorsTuan Pham, Masaaki Higashitani
Life of this patent
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Abstract
A method of making a memory array and peripheral circuits together on a single substrate forms a dielectric layer, floating gate layer, inter-layer dielectric and mask layer across all regions of the substrate. Subsequently these layers are removed from the peripheral regions and dielectrics of different thicknesses are formed in the peripheral regions according to the voltages of the circuits in these regions. A conductive layer is formed over the memory array and the peripheral circuits to form control gates in the memory array and form gate electrodes in the peripheral regions.
Claims15
A method of forming a non-volatile memory array, high-voltage circuits and logic circuits on a substrate, the array overlying a first region of the substrate, the high-voltage circuits overlying a second region of the substrate and the logic circuits overlying a third region of the substrate, comprising:
- forming a first dielectric layer that extends across the first, second and third regions;
- forming a floating gate polysilicon layer that extends over the first dielectric layer across the first, second and third regions;
- forming an inter-layer dielectric layer that extends directly over the floating gate polysilicon layer across the first, second and third regions;
- forming a mask layer that extends over the inter-layer dielectric layer across the first, second and third regions;
- subsequently forming a plurality of shallow trench isolation structures that extend into the substrate and that separate portions of the floating gate polysilicon layer;
- and
- subsequently removing portions of the floating gate polysilicon layer and portions of the mask layer overlying the second and third regions of the surface without removing portions of the floating gate polysilicon layer and portions of the mask layer that overlie the first region.
A method of forming a non-volatile memory array in an array region of a substrate, the non-volatile memory having floating gates that are self-aligned to shallow trench isolation portions and forming peripheral circuits that extend over a high-voltage region and a low-voltage region of the surface of a substrate, comprising:
- forming a floating gate dielectric layer of a first thickness that extends over the array region, high-voltage region and low-voltage region;
- forming one or more layers of floating gate material that extend directly over the floating gate dielectric layer in the array region, high-voltage region and low-voltage region;
- forming an inter-layer dielectric layer that extends directly over the one or more layers of floating gate material in the array region, high-voltage region and low-voltage region;
- forming a patterned layer of etch mask material that extends over the inter-layer dielectric layer in the array region, high-voltage region and low-voltage region;
- subsequently forming shallow trench isolation structures in the substrate surface in a pattern defined by the etch mask material, thereby dividing the one or more floating gate layers and defining an extent of a floating gate along a first direction;
- subsequently removing portions of the floating gate dielectric layer, the one or more layers of floating gate material, the inter-layer dielectric layer and the layer of etch mask material that extend over the high-voltage and low-voltage regions;
- subsequently forming a low-voltage dielectric layer of a second thickness over the low-voltage region and a high-voltage dielectric layer of a third thickness over the high-voltage region;
- and
- subsequently forming a control gate layer directly overlying the inter-layer dielectric in the array region, directly overlying the low-voltage dielectric layer in the low-voltage region and directly overlying the high-voltage dielectric layer in the high-voltage region.
A memory system on a silicon chip, comprising:
- an array of memory cells on a substrate, memory cells arranged in rows along a first direction and columns along a second direction, a memory cell having a floating gate separated from the substrate by a first dielectric layer of a first thickness, adjacent floating gates along a row separated by shallow trench isolation structures, floating gates limited in the first direction by the shallow trench isolation structures so that floating gates do not overlap shallow trench isolation structures;
- a high-voltage peripheral circuit having shallow trench isolation structures and devices that include a second dielectric layer of a second thickness;
- a low-voltage peripheral circuit having shallow trench isolation structures and devices that include a third dielectric layer of a third thickness;
- a conductive layer that extends across the array, high-voltage peripheral circuit and low-voltage peripheral circuit, the conductive layer separated from the floating gates by an inter-layer dielectric, separated from the substrate of the high-voltage peripheral circuit by the second dielectric layer and separated from the substrate of the low-voltage peripheral circuit by the third dielectric layer.
A method of forming a-non-volatile memory array, high-voltage circuits and logic circuits on a substrate, the array overlying a first region of the substrate, the high-voltage circuits overlying a second region of the substrate and the logic circuits overlying a third region of the substrate, comprising:
- forming a first dielectric layer that extends across the first, second and third regions;
- forming a floating gate polysilicon layer that extends over the first dielectric layer across the first, second and third regions;
- forming an inter-layer dielectric layer that extends directly over the floating gate polysilicon layer across the first, second and third regions;
- forming a mask layer that extends over the inter-layer dielectric layer across the first, second and third regions;
- subsequently forming a plurality of shallow trench isolation structures that extend into the substrate and that separate portions of the floating gate polysilicon layer;
- subsequently removing portions of the first dielectric layer, portions of the floating gate polysilicon layer and portions of the mask layer overlying the second and third regions of the surface without removing portions of the first dielectric layer, portions of the floating gate polysilicon layer and portions of the mask layer that overlie the first region;
- and
- subsequently forming a second dielectric layer overlying the second region and forming a third dielectric layer overlying the third region.
Dependencies are inferred from the claim text.