Method, apparatus, and system for active refresh management
AssigneeIntel Corporation
InventorsSandeep Jain, Animesh Mishra, John Halbert
Life of this patent
Estimating the term…
Abstract
A method, apparatus, and system to enable a partial refresh scheme for DRAM which includes specifying at least a refresh start value, or a refresh start value and a refresh end value, to reduce the number of rows that must be refreshed during a refresh cycle, thus reducing the amount of power consumed during refresh.
Claims53
A memory device comprising:
- an array of memory cells;
- and
- at least one readable and writable refresh start/end data storage element to store a refresh start value indicating a specific point within the array of memory cells for starting a refresh operation.
A method comprising:
- specifying a refresh start value;
- specifying a refresh end value;
- and
- refreshing a contiguous block in memory defined by the refresh start value and the refresh end value.
A method comprising:
- receiving a refresh write command;
- and
- receiving a refresh value.
A method comprising:
- receiving a refresh read command;
- reading a value from a refresh counter and storing it in a register;
- reading the value from the register;
- and
- sending the value to a memory controller device.
An apparatus comprising:
- a control unit;
- a refresh start/end register coupled to the control unit to store a refresh start value;
- and
- a refresh counter coupled to the refresh start/end register to increment or decrement a row address during a refresh cycle.
An article of manufacture comprising a machine-accessible medium having stored thereon instructions which, when executed by a machine, cause the machine to:
- specify a refresh start value;
- specify a refresh end value;
- and
- refresh a contiguous block in memory defined by the refresh start value and the refresh end value.
An article of manufacture comprising a machine-accessible medium having stored thereon instructions which, when executed by a machine, cause the machine to:
- specify a refresh start value;
- specify a fractional portion of memory;
- and
- refresh a contiguous block in memory defined by the refresh start value and the fractional portion of memory.
A system comprising:
- a processor;
- a memory controller device coupled to the processor, the memory controller device capable of sending a refresh start value and a refresh end value;
- and
- a memory device coupled to the memory controller device, the memory device capable of receiving and storing the refresh start value and the refresh end value.
A memory device comprising:
- an array of memory cells;
- at least one readable and writable data storage element to store a refresh start value indicating a specific point within the array of memory cells for starting a refresh operation;
- and
- at least one readable and writable data storage element to store a refresh end value indicating a specific point within the array of memory cells for ending a refresh operation.
Dependencies are inferred from the claim text.