Package and method for saving space required by I/O of chip
AssigneeSiliconmotion Inc.
InventorYu-Wei Chyan
Life of this patent
Estimating the term…
Abstract
A package and a method for saving space required by I/Os of a chip are described. In this method, a plurality of general I/Os and at least one special I/O are allocated in different areas. When the chip is attached to a circuit board, the special I/O is adjacent to a non-soldering area of the circuit board and the general I/Os are adjacent to a soldering area of the circuit board. The special I/O is located on the bottom surface of the chip. When the chip is attached to the circuit board, the special I/O is adjacent to a soldering resistant layer and the general I/Os are electrically connected to signal lines on the circuit board.
Claims10
A method for saving space required by I/Os of a package, the method comprising:
- allocating a plurality of general I/Os and at least one special I/O in different areas of a package of a chip;
- and
- when the chip is attached to a circuit board, placing the special I/O adjacent to a non-soldering area of the circuit board, and placing the general I/Os adjacent to a soldering area of the circuit board.
A package for saving space required by I/Os, the package comprising:
- a package layer for covering a chip;
- a plurality of general I/Os, connecting to the chip through the package;
- and
- at least one special I/O, connecting to the chip through the package;
- wherein the general I/Os and the special I/O are allocated in different areas on the surface of the package, and when the chip is attached to a circuit board, the special I/O is placed adjacent to a non-soldering area of the circuit board, and the general I/Os are placed adjacent to a soldering area of the circuit board.
Dependencies are inferred from the claim text.