Integrated circuit arrangement with NPN and PNP bipolar transistors and corresponding production method

An integrated circuit arrangement comprising:

• a NPN transistor containing an n-doped emitter region, a p-doped base region and an n-doped collector region;
• a PNP transistor containing a p-doped emitter region, an n-doped base region and a p-doped collector region;
• and
• an insulating layer on semiconductor material, the insulating layer containing:
• a first cutout below which the base region of the PNP transistor is arranged and in which electrically conductive material of an emitter connection region of the PNP transistor is arranged, the electrically conductive material connected to the emitter region of the PNP transistor, the first cutout at least one of delimiting the width of the electrical contact between the emitter connection region and the emitter region of the PNP transistor or adjoining the emitter connection region, the electrically conductive material at least one of overlapping the insulating layer or adjoining the insulating layer outside the first cutout, and
• a second cutout including the base region of the NPN transistor,
• wherein at least one of:
• at least one of the collector or emitter region of the PNP transistor has the same contour form as the first cutout, or
• at least one of the collector or emitter region of the NPN transistor has the same contour form as the second cutout.

A method for fabricating an integrated circuit arrangement that includes a NPN transistor containing an n-doped emitter region, a p-doped base region, and an n-doped collector region, and a PNP transistor containing a p-doped emitter region, an n-doped base region, and a p-doped collector region, the method, implemented without restrictions by the order prescribed, comprising:

• depositing an insulating layer on a monocrystalline semiconductor material;
• patterning the insulating layer to produce a first cutout,
• depositing a first connection layer on the patterned insulating layer, the first connection layer comprising an electrically conductive material or a material convertible into an electrically conductive material;
• patterning the first connection layer to produce an emitter connection region for the emitter region of the PNP transistor in the first cutout and to overlap the insulating layer outside the first cutout;
• providing the base region of the NPN transistor in a second cutout of the insulating layer after patterning the connection layer;
• wherein the base region of the PNP transistor is arranged below the cutout.

A method for fabricating an integrated circuit arrangement that includes a NPN transistor containing an n-doped emitter region, a p-doped base region, and an n-doped collector region, and a PNP transistor containing a p-doped emitter region, an n-doped base region, and a p-doped collector region, the method, implemented without restrictions by the order prescribed, comprising:

• depositing an insulating layer on a monocrystalline semiconductor material;
• patterning the insulating layer to produce a first cutout,
• depositing a first connection layer on the patterned insulating layer, the first connection layer comprising an electrically conductive material or a material convertible into an electrically conductive material;
• patterning the first connection layer to produce an emitter connection region for the emitter region of the PNP transistor in the first cutout and to overlap the insulating layer outside the first cutout;
• providing the base region of the NPN transistor in a second cutout of the insulating layer after patterning the connection layer;
• wherein the base region of the PNP transistor is arranged below the cutout, and at least one of:
• at least one of the collector or emitter region of the PNP transistor has the same contour form as the first cutout, or
• at least one of the collector or emitter region of the NPN transistor has the same contour form as the second cutout.

An integrated circuit arrangement comprising:

• a NPN transistor containing an n-doped emitter region, a p-doped base region and an n-doped collector region;
• a PNP transistor containing a p-doped emitter region, an n-doped base region and a p-doped collector region;
• and
• means for insulating semiconductor material forming the base region of the NPN transistor and the PNP transistor from overlying layers;
• first means for connecting to the emitter region of the PNP transistor;
• and
• second means for connecting to the emitter region of the NPN transistor.