Semiconductor devices and methods of forming interconnection lines therein

A method of forming an interconnection line of a semiconductor device, comprising:

• sequentially forming a metal layer and a conductive layer on a semiconductor substrate including a lower interlayer insulating layer;
• forming a first conductive layer pattern including a hole to partially expose the metal layer by patterning the conductive layer;
• forming a mask pattern which fills the hole of the first conductive layer pattern and masks the first conductive layer pattern around the hole;
• dividedly forming a second conductive layer pattern by etching the first conductive layer pattern using the mask pattern;
• forming a first metal layer pattern including a protruding portion by partially etching the metal layer up to a predetermined thickness with the use of both the mask pattern and the second conductive layer pattern;
• removing the mask pattern;
• forming a spacer on a sidewall of each the second conductive layer pattern and the protruding portion of the first metal layer pattern;
• and
• forming a lower wire comprising the second conductive layer pattern and a second metal layer pattern, the second metal layer pattern being dividedly formed by etching the first metal layer pattern with the use of the spacer.