CMOS thin film transistor comprising common gate, logic device comprising the CMOS thin film transistor, and method of manufacturing the CMOS thin film transistor

An inverter including a CMOS thin film transistor, the CMOS thin film transistor comprising:

• a P-channel transistor;
• an N-channel transistor intersecting the P-channel transistor, the N-channel and the P-channel transistor having a common gate;
• a base substrate;
• and
• a semiconductor layer formed on the base substrate,
• wherein the P-channel transistor and the N-channel transistor are formed on the semiconductor layer, and a Schottky barrier inducing material layer is formed on surfaces of a source and a drain of one of the P-channel transistor and the N-channel transistor.

A NOR logic device including two CMOS thin film transistors, each of the CMOS thin film transistors comprising:

• a P-channel transistor;
• an N-channel transistor intersecting the P-channel transistor, the N-channel and the P-channel transistor having a common gate;
• a base substrate;
• and
• a semiconductor layer formed on the base substrate,
• wherein the P-channel transistor and the N-channel transistor are formed on the semiconductor layer, and a Schottky barrier inducing material layer is formed on surfaces of a source and a drain of one of the P-channel transistor and the N-channel transistor.

A NAND logic device including two CMOS thin film transistors, each of the CMOS thin film transistors comprising:

• a P-channel transistor;
• an N-channel transistor intersecting the P-channel transistor, the N-channel and the P-channel transistor having a common gate;
• a base substrate;
• and
• a semiconductor layer formed on the base substrate,
• wherein the P-channel transistor and the N-channel transistor are formed on the semiconductor layer, and a Schottky barrier inducing material layer is formed on surfaces of a source and a drain of one of the P-channel transistor and the N-channel transistor.

A method of forming a semiconductor device, the method comprising:

• forming a semiconductor layer on a base substrate;
• defining a first area where a P-channel transistor is formed and a second area where an N-channel transistor is formed, within the semiconductor layer;
• patterning the semiconductor layer to produce the first and second areas;
• forming the P-channel transistor and the N-channel transistor on the first and second areas, respectively;
• forming a Schottky barrier inducing material layer on surfaces of a source and a drain of one of the P-channel transistor and the N-channel transistor;
• and
• forming a common gate on an area where the P-channel and N-channel transistors intersect.