Semiconductor devices having buried bit lines and methods of manufacturing semiconductor devices having buried bit lines

A unit cell of a semiconductor memory device, comprising:

• a semiconductor substrate having a first conductivity type and having an upper portion;
• a pair of bit lines doped with an impurity of a second conductivity type opposite to the first conductivity type and spaced from one another in the upper portion of the semiconductor substrate;
• a channel region between the pair of bit lines, the channel region having an upper surface and a pair of opposing side surfaces;
• a pair of recess regions adjacent the opposing side surfaces of the channel region, the recess regions isolating the pair of bit lines on either side of the channel region;
• and
• a gate electrode formed above the upper surface and side surfaces of the channel region.

A semiconductor device, comprising:

• a semiconductor substrate having a first conductivity type and having an upper portion;
• at least one pair of bit lines extending in a first direction, the at least one pair of bit lines doped with an impurity of a second conductivity type opposite to the first conductivity type and spaced from one another in the upper portion of the semiconductor substrate;
• a first line formed between the at least one pair of bit lines comprising a plurality of alternating channel regions and recessed device isolation regions, each of the channel regions contacting each bit line of the at least one pair of bit lines;
• and
• a plurality of word lines formed at right angles to the bit lines and covering the channel regions.