Structure of semiconductor substrate including test element group wiring
AssigneeRohm Co., Ltd.
InventorsTakashi Nasuno, Hiroshi Tsuda
Life of this patent
Estimating the term…
Abstract
A structure of test element group wiring includes, in addition to an electrode on a substrate including one or more layers of insulating films, and real wirings electrically connected to the electrode, includes dummy wirings electrically isolated from the electrode and having a portion of the same shape as the real wiring. The dummy wirings are disposed at a predetermined constant distance, adjacent to the real wirings or to each other, so that the wiring rate of the real wiring relaxes the concentration difference of patterns. The distance between the real wirings is sufficient to perform pattern analysis using the OBIRCH method.
Claims7
1-6. (canceled)
A semiconductor substrate comprising:
- a substrate including at least one layer of an insulating film,
- a scribe line area dividing said substrate into a plurality of chip regions,
- a plurality of semiconductor chips in respective chip regions defined by said scribe line area, and
- a test element group (TEG) wiring in the scribe line area, wherein said TEG wiring includes:
- an electrode on said substrate,
- a real wiring electrically connected to said electrode, and
- a plurality of dummy wirings electrically isolated from said electrode, disposed at constant intervals said real wiring, and having a portion of the same shape as said real wiring.
Dependencies are inferred from the claim text.