Electrostatic discharge protection circuit using triple welled silicon controlled rectifier
AssigneeElectronics and Telecommunications Research Institute
InventorsKwi Kim, Chong Kwon, Jong Kim
Life of this patent
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Abstract
Provided is an electrostatic discharge (ESD) protection circuit using a silicon controlled rectifier (SCR), which is applied to a semiconductor integrated circuit (IC). A semiconductor substrate has a triple well structure such that a bias is applied to a p-well corresponding to a substrate of a ggNMOS device. Thus, a trigger voltage of the SCR is reduced. In addition, two discharge paths are formed using two SCRs comprised of PNP and NPN bipolar transistors, with the result that the ESD protection circuit can have great discharge capacity.
Claims9
An electrostatic discharge protection circuit using a silicon controlled rectifier, the circuit comprising:
- a semiconductor substrate including a first well, a second well, a third well, and a fourth well being formed in the first well;
- first and second heavily doped regions formed in an upper portion of the second well;
- third, fourth, and fifth heavily doped regions formed in an upper portion of the third well;
- sixth and seventh heavily doped regions formed in an upper portion of the fourth well;
- an eighth heavily doped region formed at an interface between the second and third wells;
- a ninth heavily doped region formed at an interface between the third and fourth wells;
- a first gate formed on the semiconductor substrate between the third and eighth heavily doped regions and electrically insulated from the semiconductor substrate by a gate insulating layer;
- and
- a second gate formed on the semiconductor substrate between the fifth and ninth heavily doped regions and electrically insulated from the semiconductor substrate by the gate insulating layer.
An electrostatic discharge protection circuit using a silicon controlled rectifier, the circuit comprising:
- first and second transistors connected in parallel between first and second terminals;
- a first resistor connected to gates of the first and second transistors;
- second and third resistors connected in parallel to the first terminal;
- a third transistor having an emitter connected to the first resistor and having a base connected to the second and third resistors;
- a fourth resistor connected between a collector of the third transistor and a ground;
- fourth and fifth transistors connected in parallel between the second terminal and the base of the third transistor and each having a base connected to the emitter of the third transistor;
- and
- sixth and seventh transistors connected in parallel between the first terminal and the emitter of the third transistor and each having a gate connected to the base of the third transistor.
Dependencies are inferred from the claim text.