Methods of fabricating flash memory devices having self-aligned floating gate electrodes and related devices

A method of fabricating a semiconductor memory device, the method comprising:

• forming an active region protruding from a semiconductor substrate;
• forming an isolation layer on the substrate adjacent opposing sidewalls of the active region;
• forming a floating gate electrode on the active region and extending beyond opposite edges thereof onto the isolation layer, wherein edge portions of the floating gate electrode on the isolation layer extend towards the substrate at least as far as a central portion of the floating gate electrode on the active region;
• and
• forming a control gate electrode on a surface of the floating gate electrode opposite the active region and extending along sidewalls of the floating gate electrode towards the substrate beyond a surface of the floating gate electrode adjacent the active region.

A method of fabricating a semiconductor memory device, the method comprising:

• forming a mask pattern on a semiconductor substrate;
• patterning the substrate using the mask pattern to define an active region therein;
• forming an isolation layer on the substrate along opposing sidewalls of the active region and the mask pattern;
• removing the mask pattern to define a groove in the isolation layer extending beyond edges of a surface of the active region between the opposing sidewalls thereof;
• forming a floating gate conductive layer on the isolation layer and in the groove;
• removing portions of the floating gate conductive layer outside of the groove to define a floating gate electrode confined within the groove;
• recessing the isolation layer towards the substrate beyond a surface of the floating gate electrode adjacent the active region using the floating gate electrode as a mask;
• and
• forming a control gate electrode on the floating gate electrode opposite the active region and extending into the recessed isolation layer beyond the surface of the floating gate electrode adjacent the active region,
• wherein the control gate electrode and the floating gate electrode are electrically isolated.

A semiconductor memory device, comprising:

• a semiconductor substrate including an active region protruding therefrom;
• an isolation layer on the substrate adjacent opposing sidewalls of the active region;
• a floating gate electrode on a surface of the active region between the opposing sidewalls thereof and extending beyond edges of the surface of the active region onto the isolation layer, wherein a surface of the floating gate electrode adjacent the active region defines a plane, and wherein the isolation layer is confined between the plane and the substrate;
• and
• a control gate electrode on a surface of the floating gate electrode opposite the active region and extending along sidewalls of the floating gate electrode towards the substrate beyond the plane defined by the surface of the floating gate electrode adjacent the active region.

A semiconductor memory device, comprising:

• a semiconductor substrate including an active region therein protruding therefrom;
• an isolation layer on the substrate adjacent opposing sidewalls of the active region;
• a floating gate electrode on the active region and extending beyond opposite edges thereof onto the isolation layer, wherein edge portions of the floating gate electrode on the isolation layer extend towards the substrate at least as far as a central portion of the floating gate electrode on the active region;
• and
• a control gate electrode on a surface of the floating gate electrode opposite the active region and extending along sidewalls of the floating gate electrode towards the substrate beyond a surface of the floating gate electrode adjacent the active region.