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US 2006/0124985 A1Published application
Methods of forming in package integrated capacitors and structures formed thereby
OwnerXiang Zeng, Jiangqi He +1inventors
InventorsXiang Zeng, Jiangqi He, Jack Zhong
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Abstract
Methods of forming a microelectronic structure are described. Those methods comprise depositing a bottom electrode, depositing a dielectric layer on the bottom electrode, forming at least one via in the dielectric layer, wherein a bottom surface of the via does not contact a top surface of the bottom electrode, and depositing a top electrode on the dielectric layer.
Claims12
A structure comprising:
- a bottom electrode;
- a dielectric layer disposed on the bottom electrode;
- at least one via in the dielectric layer, wherein a bottom surface of the via does not contact a top surface of the bottom electrode;
- and
- a top electrode disposed on the dielectric layer.
2 more elements
A structure comprising:
- a capacitor on a substrate of a package, the capacitor comprising:
- a bottom electrode disposed on a substrate of a package;
- a dielectric layer disposed on the bottom electrode;
- at least one via in the dielectric layer, wherein a bottom surface of the via does not contact a top surface of the bottom electrode;
- and
- a top electrode disposed on the dielectric layer.
3 more elements
A system comprising:
- a capacitor structure on a substrate of a package, the capacitor structure comprising:
- at least one via in a dielectric layer, wherein a bottom surface of the via does not contact a top surface of a bottom electrode;
- a bus communicatively coupled to the capacitor structure;
- and
- a DRAM communicatively coupled to the bus.
2 more elements
Dependencies are inferred from the claim text.