Dual work function gate in CMOS device

A semiconductor device comprising:

• a first silicon layer having first and second electrodes formed therein;
• a gate oxide formed over the first silicon layer;
• and,
• a second silicon layer formed over the gate oxide, wherein the second silicon layer comprises a dual work function gate having differently doped regions of substantially equal areas.

A method of making a transistor comprising:

• forming a buried oxide layer over a first silicon layer;
• forming a second silicon layer over the buried oxide layer such that the second silicon layer includes a source region and a drain region separated by a channel region;
• forming a gate oxide formed over the channel region of the second silicon layer;
• and,
• forming a third silicon layer over the gate oxide such that the third silicon layer includes a dual work function gate having regions of differing conductivity.

A transistor comprising:

• a first silicon layer having a source region and a drain region separated by a channel region;
• a gate oxide formed over the channel region of the first silicon layer;
• and,
• a second silicon layer formed over the gate oxide, wherein the second silicon layer includes a dual work function gate comprising first and second gate regions, wherein the first and second gate regions each has a lateral dimension and a transverse dimension, wherein the lateral dimension extends parallel to the source and drain regions, wherein the transverse dimension extends perpendicularly to the source and drain regions, and wherein the lateral dimension is greater than the transverse dimension.